用于32单元串电阻式RAM阵列的高离子/开关比BJT选择器

A. Redaelli, L. Laurin, S. Lavizzari, C. Cupeta, G. Servalli, A. Benvenuti
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引用次数: 1

摘要

任何阻性RAM阵列都需要一个紧凑的低泄漏选择器来实现正确的内存操作。由于基于焦耳加热的编程机制,相变存储器在低泄漏和驱动电流能力之间的权衡方面要求很高。这项工作解决了优化双极结晶体管(BJT)的完整集成路径,以实现长达32的基极-发射极结长串,从而减少基极带开销,从而进一步减少相对于传统方法的有效阵列尺寸。基极电阻值与基极漏极之间的优化并不简单,主要是通过TCAD对结位和工艺热预算进行优化。在45 nm的PCM载体上进行了实验验证,证明了该方法的可行性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High Ion/Ioff ratio BJT selector for 32 cell string Resistive RAM arrays
A compact low leakage selector is needed for any resistive RAM arrays to enable the correct memory operation. In particular Phase Change Memories are demanding in terms of trade off between low leakage and driving current capability due to the Joule-heating-based programming mechanism. This work addresses a full integration path for optimizing bipolar junction transistor (BJT) to realize long string of base-emitter junctions up to 32, enabling the reduction of the base straps overhead thus further reducing the effective array size in respect to conventional approach. The optimization between the base resistance value and base-emitter leakage is not trivial and it has been performed by working on junction position and process thermal budget mainly by TCAD. Experimental validation has been provided on a 45 nm PCM vehicle, demonstrating the feasibility of the proposed approach.
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