2014 44th European Solid State Device Research Conference (ESSDERC)最新文献_第8页

Data regeneration and disturb immunity of T-RAM cells T-RAM细胞的数据再生和干扰免疫

2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948754

H. Mulaosmanovic, C. M. Compagnoni, Niccolo Castellani, Gianpietro Carnevale, D. Ventrice, P. Fantini, A. Spinelli, A. Lacaita, Augusto Benvenuti

引用次数: 4

Improved low-frequency noise for 0.3nm EOT thulium silicate interfacial layer 改善了0.3nm EOT硅酸铥界面层的低频噪声

2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948835

M. Olyaei, B. Malm, E. Litta, P. Hellström, M. Östling

引用次数: 1

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies 电路和工艺协同设计与垂直栅极全方位纳米线场效应管技术，以扩展CMOS缩放5nm及以上的技术

2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948768

T. H. Bao, D. Yakimets, J. Ryckaert, I. Ciofi, R. Baert, A. Veloso, J. Bömmels, N. Collaert, P. Roussel, S. Demuynck, P. Raghavan, A. Mercha, Z. Tokei, D. Verkest, A. Thean, P. Wambacq

{"title":"Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies","authors":"T. H. Bao, D. Yakimets, J. Ryckaert, I. Ciofi, R. Baert, A. Veloso, J. Bömmels, N. Collaert, P. Roussel, S. Demuynck, P. Raghavan, A. Mercha, Z. Tokei, D. Verkest, A. Thean, P. Wambacq","doi":"10.1109/ESSDERC.2014.6948768","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948768","url":null,"abstract":"This paper presents a vertical gate-all-around nanowire FET (VFET) architecture targeting 5nm and beyond technologies, and a new standard-cell construct for digital flow implementation. VFET technology circuits and parasitics for processes and design features aligned with 5nm CMOS are systematically assessed for the first time. Self-aligned quadruple pattering (SAQP) is implemented to achieve required 12nm half-pitch interconnects, and the worst case RC delay corner is 1.4X slower than best case corner. Our work shows that interconnect delay variability of a wire of average length in SoCs can overwhelm device variability. Consequently, a new device architecture with a smaller footprint as VFET would effectively lower the BEOL variability by shortening the wirelength and help SRAM bit cells to follow 50% area scaling trend. It is shown that a VFET-based D Flip-Flop (DFF) and 6T-SRAM cell can offer 30% smaller layout area than FinFET (or equivalent lateral 2D) based designs. Furthermore, we obtain a 19% reduction in routing area of a 32-bit multiplier implemented with a VFET-based standard-cell library w.r.t. the FinFET design.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125842680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 34

Compact Fermi potential model for heterostructure HEMTs with rectangular quantum well 矩形量子阱异质结构hemt的紧凑费米势模型

2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948811

A. Ajaykumar, Xing Zhou, B. Syamal, S. B. Chiah

引用次数: 4

Two dimensional quantum mechanical simulation of low dimensional tunneling devices 低维隧穿装置的二维量子力学模拟

2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948791

C. Alper, P. Palestri, L. Lattanzio, J. Padilla, A. Ionescu

引用次数: 17

Physical model for GaN HEMT design optimization in high frequency switching applications 高频开关应用中GaN HEMT设计优化的物理模型

2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948843

D. Cucak, M. Vasić, Ó. García, Y. Bouvier, J. Oliver, P. Alou, J. Cobos, A. Wang, S. Martin-Horcajo, F. Romero, F. Calle

{"title":"Physical model for GaN HEMT design optimization in high frequency switching applications","authors":"D. Cucak, M. Vasić, Ó. García, Y. Bouvier, J. Oliver, P. Alou, J. Cobos, A. Wang, S. Martin-Horcajo, F. Romero, F. Calle","doi":"10.1109/ESSDERC.2014.6948843","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948843","url":null,"abstract":"In this paper, physical modeling of a GaN HEMT is proposed, with the objective of device design optimization for application in a high frequency DC/DC converter. From the point of view of a switching application, physical model for input, output and reverse capacitance as well as for channel resistance is very important, since the aforementioned parameters determine power losses in the circuit. The obtained physical model of the switching device can be used for simulation models such as PSpice or hybrid behavioral power loss models for high frequency DC/DC converters. In this work, extrinsic model for Id (Vds, Vgs) output characteristics of a depletion mode GaN HEMT with a field plate structure was obtained, as well as physical model for input, output and reverse capacitance in the subthreshold regime. The model was implemented in Simplorer simulation model and verified by the measured efficiency curves of the buck converter prototype, using the GaN HEMT that was analyzed. With the increase of the switching frequency, precision of the model increases, especially in the low power area, which is the area of interest in our application.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122561980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

The effect of the surface fixed charge and donor traps on the C(V) and transfer characteristics of a GaN MISFET — Experiment and TCAD simulations 表面固定电荷和施主陷阱对GaN MISFET C(V)和转移特性的影响-实验和TCAD模拟

2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948827

G. Longobardi, F. Udrea, S. Sque, J. Croon, F. Hurkx, J. Sonsky

引用次数: 6

Study of low frequency noise in advanced SiGe:C heterojunction bipolar transistors 先进SiGe:C异质结双极晶体管低频噪声研究

2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948838

M. Seif, F. Pascal, B. Sagnes, A. Hoffmann, S. Haendler, P. Chevalier, D. Gloria

{"title":"Study of low frequency noise in advanced SiGe:C heterojunction bipolar transistors","authors":"M. Seif, F. Pascal, B. Sagnes, A. Hoffmann, S. Haendler, P. Chevalier, D. Gloria","doi":"10.1109/ESSDERC.2014.6948838","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948838","url":null,"abstract":"The purpose of this work is to characterize and locate the low frequency noise sources in advanced SiGe:C Heterojunction Bipolar Transistor (HBTs) developed for mm-Wave and THz applications. Low frequency noise is studied over transistors with different emitter areas (Ae) and emitter perimeters (Pe) at different base current biases. The 1/f noise level shows a quadratic evolution with base current IB and 1/Ae, dependence versus emitter areas. Moreover the 1/f noise level is found to be independent of the emitter perimeter Pe. It is found that the low frequency noise sources are homogenously distributed in the base-emitter region. The SPICE parameter KF related to the 1/f noise amplitude as well as the figure of merit Kb are found to be among the best results published. For instance Kb values lower than 10-10 μm2 are found. Compare to others bipolar technologies, very good values of the ratio fc/ft are found underlining the quality of this advanced one. A minority of the transistors, mainly for small emitter areas, are affected by the presence of generation-recombination (g-r) components.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127175734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Analytical modelling and leakage optimization in complementary resistive switch (CRS) crossbar arrays 互补电阻开关(CRS)交叉栅阵列的解析建模与泄漏优化

2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948805

S. Ambrogio, S. Balatti, D. Ielmini, D. Gilmer

引用次数: 2

Low frequency MOS-CV technique for selfconsistent determination of dark currents in high resistivity substrates 自一致测定高电阻率衬底暗电流的低频MOS-CV技术

2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948845

R. Sorge, J. Quick, P. Schley, D. Bolze, T. Grabolla

引用次数: 0