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Advanced TCAD for predictive FinFETs Vth mismatch using full 3D process/device simulation 先进的TCAD预测finfet Vth失配使用全3D工艺/器件模拟
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948830
E. Bazizi, A. Zaka, T. Herrmann, F. Benistant, J. H. Tin, J. P. Goh, L. Jiang, M. Joshi, H. Meer, K. Korablev
{"title":"Advanced TCAD for predictive FinFETs Vth mismatch using full 3D process/device simulation","authors":"E. Bazizi, A. Zaka, T. Herrmann, F. Benistant, J. H. Tin, J. P. Goh, L. Jiang, M. Joshi, H. Meer, K. Korablev","doi":"10.1109/ESSDERC.2014.6948830","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948830","url":null,"abstract":"Predictive TCAD tool is crucial for several reasons such as to provide pre-silicon data, shorten the technology development cycle and reduce the fabrication cost. In this paper, advanced 3D TCAD process and device simulations is used to gain physical understanding and to optimize the performance/variability of bulk-FinFETs. For the first time, the full FinFET process flow simulation was performed using diffusion, activation and segregation models identical to those used in planar nodes. In this work a wide range of implantation and anneal splits is used to demonstrate the 3D simulation accuracy. After achieving good agreement with experiments in terms of Vth and Ion/Ioff, considering lateral dopant diffusion and activation, the simulation was used to investigate SRAM random doping fluctuation RDF.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129555692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Investigation of partially gated Si tunnel FETs for low power integrated optical sensing 用于低功耗集成光传感的部分门控硅隧道场效应管的研究
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948792
N. Dagtekin, A. Ionescu
{"title":"Investigation of partially gated Si tunnel FETs for low power integrated optical sensing","authors":"N. Dagtekin, A. Ionescu","doi":"10.1109/ESSDERC.2014.6948792","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948792","url":null,"abstract":"This paper presents experimental results regarding optical and electrical characteristics of a partially gated p-i-n structure that has an extension in the channel region coated with transparent material. The correlation between band to band tunneling and photo current is discussed. Four main phenomena are observed under illumination: (1) negative transconductance can be obtained under reverse bias conditions (2) the off current is governed by the photocurrent and subthreshold slope is degraded (3) a kink in the saturation current appears in the output characteristics (4) the light sensitivity of the transconductance in P mode operation can be tuned with the back gate bias.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116366139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A positive impact of low proton irradiation energy on oxynitride gate 4H-SiC MOSFETs 低质子辐照能量对氮化氧栅4H-SiC mosfet的积极影响
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948780
M. Florentin, J. Millán, P. Godignon, M. Alexandru, A. Constant, B. Schmidt
{"title":"A positive impact of low proton irradiation energy on oxynitride gate 4H-SiC MOSFETs","authors":"M. Florentin, J. Millán, P. Godignon, M. Alexandru, A. Constant, B. Schmidt","doi":"10.1109/ESSDERC.2014.6948780","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948780","url":null,"abstract":"The electrical response of lateral 4H-SiC MOSFET with different thicknesses of N2O gate oxide, and submitted to different irradiation fluences under 0.18 MeV proton energy is reported. After being firstly measured with the time bias stress instability technique (BSI), the MOSFETs were submitted to a short thermal annealing at 120oC for 14h. Regardless the irradiation and the very short annealing time, significant differences with respect to Silicon-irradiated MOSFET have been observed. We associated these differences to the diffusion of nitrogen atoms inside the SiC epilayer but also, to the mobile ion charge tunneling from the same epilayer into the oxide, especially during the annealing process. Finally, if the oxide thickness and the irradiation fluence are balanced, the SiC MOSFET performance can be enhanced, operating in high temperature and harsh environments.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116769031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Monte Carlo modeling of the extraction of roughness parameters at nanometer scale by Critical Dimension Scanning Electron Microscopy 临界维数扫描电镜提取纳米尺度粗糙度参数的蒙特卡罗建模
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948834
M. Ciappa, Emre Ilgünsatiroglu, A. Illarionov, F. Filosomi, C. Santini
{"title":"Monte Carlo modeling of the extraction of roughness parameters at nanometer scale by Critical Dimension Scanning Electron Microscopy","authors":"M. Ciappa, Emre Ilgünsatiroglu, A. Illarionov, F. Filosomi, C. Santini","doi":"10.1109/ESSDERC.2014.6948834","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948834","url":null,"abstract":"Uncertainties in the sub-nanometer range, the use of new materials, roughness, and the three-dimensional structures represent main challenges for the metrology of critical dimensions in nanostructures. In this paper, Monte Carlo modeling is used to investigate the correlation of the “true line edge roughness” of photoresist lines with the roughness rendered by Critical Dimension Scanning Electron Microscopy. Examples are presented, where realistic full-three dimensional photoresist structures in the nanometer range are generated by TCAD process simulation.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121843289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A high-sensitivity 135GHz millimeter-wave imager by differential transmission-line loaded split-ring-resonator in 65nm CMOS 采用差分传输在线加载分环谐振器的高灵敏度135GHz毫米波成像仪
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948786
Y. Shang, Hao Yu, Chang Yang, Sanming Hu, M. Je
{"title":"A high-sensitivity 135GHz millimeter-wave imager by differential transmission-line loaded split-ring-resonator in 65nm CMOS","authors":"Y. Shang, Hao Yu, Chang Yang, Sanming Hu, M. Je","doi":"10.1109/ESSDERC.2014.6948786","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948786","url":null,"abstract":"A high-sensitivity 135GHz millimeter-wave (mm-wave) imager is demonstrated in 65nm CMOS by on-chip metamaterial resonator: a differential transmission-line (T-line) loaded with split-ring-resonator (DTL-SRR). Due to sharp stop-band introduced by metamaterial load, high-Q oscillatory amplification can be achieved with high sensitivity when utilizing DTL-SRR as quench-controlled oscillator to provide regenerative detection. The developed mm-wave imager pixel has a compact core chip area of 0.0085mm2 with measured power consumption of 6.2mW, sensitivity of -76.8dBm, noise figure of 9.7dB, and noise equivalent power of 0.9fW/√Hz with demonstrated mm-wave images.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131532473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Non-homogeneous space mechanical strain induces asymmetrical magneto-tunneling conductance in MOSFETs 非均匀空间机械应变诱导mosfet的非对称磁隧电导
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948765
A. E. P. D. los, E. Gutiérrez-D., J. Reyes, F. Guarín
{"title":"Non-homogeneous space mechanical strain induces asymmetrical magneto-tunneling conductance in MOSFETs","authors":"A. E. P. D. los, E. Gutiérrez-D., J. Reyes, F. Guarín","doi":"10.1109/ESSDERC.2014.6948765","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948765","url":null,"abstract":"Through the measurement of the magneto-conductance properties of the reverse-biased Drain-Bulk (DB) junction of a MOSFET, we found the conductance of the active channel region, nearby the DB junction, is not space homogeneous, but it shows better conductance properties towards the edges than in the middle of the channel. Such a non-homogeneous channel conductance is attributed to the asymmetrical distribution of the mechanical strain used to enhance the carrier mobility.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133766565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FDSOI molecular flash cell with reduced variability for low power flash applications FDSOI分子闪光电池与降低可变性低功率闪光应用
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948833
V. Georgiev, S. Amoroso, Laia Vilà‐Nadal, Cristoph Busche, L. Cronin, A. Asenov
{"title":"FDSOI molecular flash cell with reduced variability for low power flash applications","authors":"V. Georgiev, S. Amoroso, Laia Vilà‐Nadal, Cristoph Busche, L. Cronin, A. Asenov","doi":"10.1109/ESSDERC.2014.6948833","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948833","url":null,"abstract":"In this work we present a modeling study of a conceptual low power non-volatile memory cell based on inorganic molecular metal oxide clusters (polyoxometalates (POM)) as a storage media embedded in the gate dielectric of a Fully Depleted SOI (FD SOI) with reduced statistical variability. The simulations were carried out using a multi-physics simulation framework, which allows us to evaluate the variability in the programming window of the molecular based flash cell with an 18 nm gate length. We have focused our study on the threshold voltage variability influenced by random dopant fluctuations and random special fluctuations of the molecules in the floating gate of the flash-cell. Our simulation framework and conclusions can be applied not only to POM-based flash cell but also to flash cells based on alternative molecules used as a storage media.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133249735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Manufacturing of 3D integrated sensors and circuits 3D集成传感器和电路制造
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948785
M. Schrems, J. Siegert, Peter Dorfi, J. Kraft, E. Stueckler, F. Schrank, S. Selberherr
{"title":"Manufacturing of 3D integrated sensors and circuits","authors":"M. Schrems, J. Siegert, Peter Dorfi, J. Kraft, E. Stueckler, F. Schrank, S. Selberherr","doi":"10.1109/ESSDERC.2014.6948785","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948785","url":null,"abstract":"3D integration of functions such as sensors and circuit elements enables miniaturized and cost-effective smart systems. Wirebonds are replaced by Through Silicon Vias (TSVs) and Wafer Level Packaging (WLP) for shorter conductive paths and reduced form factor. This paper reviews prior art and presents a comprehensive set of data from volume manufacturing of 3D integrated optical sensors and circuits using a “via last” manufacturing flow. 3D specific yield detracting processes such as patterning of open TSVs, wafer bonding, and etching are analyzed and discussed. Functional test yields equivalent to standard CMOS process yields can be achieved.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130473247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs 双通道(sSOI衬底，SiGe沟道)平面FDSOI mosfet的应变和布局管理
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948769
F. Andrieu, M. Cassé, E. Baylac, P. Perreau, O. Nier, D. Rideau, R. Berthelon, F. Pourchon, A. Pofelski, B. D. Salvo, C. Gallon, V. Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, V. Barral, R. Ranica, N. Planes, W. Schwarzenbach, E. Richard, E. Josse, O. Weber, F. Arnaud, M. Vinet, O. Faynot, M. Haond
{"title":"Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs","authors":"F. Andrieu, M. Cassé, E. Baylac, P. Perreau, O. Nier, D. Rideau, R. Berthelon, F. Pourchon, A. Pofelski, B. D. Salvo, C. Gallon, V. Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, V. Barral, R. Ranica, N. Planes, W. Schwarzenbach, E. Richard, E. Josse, O. Weber, F. Arnaud, M. Vinet, O. Faynot, M. Haond","doi":"10.1109/ESSDERC.2014.6948769","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948769","url":null,"abstract":"We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133447679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Hybrid Systems in foil (HySiF) exploiting ultra-thin flexible chips 利用超薄柔性芯片的混合箔系统(HySiF)
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948797
C. Harendt, Zili Yu, J. Burghartz, J. Kostelnik, A. Kugler, S. Saller
{"title":"Hybrid Systems in foil (HySiF) exploiting ultra-thin flexible chips","authors":"C. Harendt, Zili Yu, J. Burghartz, J. Kostelnik, A. Kugler, S. Saller","doi":"10.1109/ESSDERC.2014.6948797","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948797","url":null,"abstract":"Electronics embedded in foil is an enabling technology for flexible electronics and for special form factors of electronic components. In contrast to strictly printed electronics, Hybrid Systems-in-Foil (HySiF), comprising thin flexible, embedded chips and large-area thin-film electronic elements, feature a versatile and reliable technological solution for industrial applications of flexible electronics. This paper provides a comprehensive overview of HySiF technology, including aspects of thin-chip fabrication, reliability and assembly. Also presented is an industrial demonstrator utilizing such a HySiF component.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133698665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
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