2014 44th European Solid State Device Research Conference (ESSDERC)最新文献

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FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration FDSOI底部mosfet稳定性与具有3D单片集成的顶部晶体管热预算
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948770
C. Fenouillet-Béranger, B. Previtali, P. Batude, F. Nemouchi, M. Cassé, X. Garros, L. Tosti, N. Rambal, D. Lafond, H. Dansas, L. Pasini, L. Brunet, F. Deprat, M. Grégoire, M. Mellier, M. Vinet
{"title":"FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration","authors":"C. Fenouillet-Béranger, B. Previtali, P. Batude, F. Nemouchi, M. Cassé, X. Garros, L. Tosti, N. Rambal, D. Lafond, H. Dansas, L. Pasini, L. Brunet, F. Deprat, M. Grégoire, M. Mellier, M. Vinet","doi":"10.1109/ESSDERC.2014.6948770","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948770","url":null,"abstract":"To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400°C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124223330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Impact of crystallographic orientation and impurity scattering in Graphene-Base Heterojunction Transistors for Terahertz Operation 太赫兹工作中石墨烯基异质结晶体管晶体取向和杂质散射的影响
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948823
V. D. Lecce, R. Grassi, A. Gnudi, E. Gnani, S. Reggiani, G. Baccarani
{"title":"Impact of crystallographic orientation and impurity scattering in Graphene-Base Heterojunction Transistors for Terahertz Operation","authors":"V. D. Lecce, R. Grassi, A. Gnudi, E. Gnani, S. Reggiani, G. Baccarani","doi":"10.1109/ESSDERC.2014.6948823","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948823","url":null,"abstract":"The influence of the crystal orientation on the performance of silicon-based Graphene-Base Heterojunction Transistors (GBHTs) for terahertz operation is investigated by means of an in-house developed simulator based on quantum transport coupled with Poisson equation. The effect of impurity scattering is included, finding that terahertz operation is possible even considering the reduction of the mobility due to dopants.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124923154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Set/reset statistics and kinetics in phase change memory arrays 在相变存储器阵列中设置/重置统计数据和动力学
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948803
M. Rizzi, N. Ciocchini, D. Ielmini, A. Ghetti, P. Fantini
{"title":"Set/reset statistics and kinetics in phase change memory arrays","authors":"M. Rizzi, N. Ciocchini, D. Ielmini, A. Ghetti, P. Fantini","doi":"10.1109/ESSDERC.2014.6948803","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948803","url":null,"abstract":"The development of next-generation PCM arrays requires a better understanding of set/reset processes at statistical level. This work presents experimental programming characteristics on 45 nm arrays and analyzes the statistical distribution of set/reset program and read currents. Results show (i) a reset-voltage dependence for both the melt current and the crystallization kinetics and (ii) a reduced crystallization spread in the high-temperature (set) regime, compared to the low-temperature (retention) one.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131661849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Freeform and flexible electronics manufacturing using R2R printing and hybrid integration techniques 使用R2R打印和混合集成技术的自由形状和柔性电子制造
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948794
J. Hast, Sami Ihme, Jukka-Tapani Mäkinen, K. Keränen, M. Tuomikoski, K. Ronka, H. Kopola
{"title":"Freeform and flexible electronics manufacturing using R2R printing and hybrid integration techniques","authors":"J. Hast, Sami Ihme, Jukka-Tapani Mäkinen, K. Keränen, M. Tuomikoski, K. Ronka, H. Kopola","doi":"10.1109/ESSDERC.2014.6948794","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948794","url":null,"abstract":"Printed electronics and other large-area roll-roll - compatible processes are opening up the new opportunity for cost-efficient mass manufacturing of electronics among other functionalities, on large-area and flexible substrates such as plastic, paper, metal foils, glass and fabrics. Data processing power and other functionalities still require high performance microelectronics circuits and therefore, also traditional electronic/semiconductor technology are also needed. These needs lead to technical manufacturing requirements that can be fulfilled best with concept of utilization combination of printed electronics and hybrid integration of silicon electronics to flexible printed platforms. Extending the continuous roll-to-roll manufacturing approach as far as possible (in air or/and in vacuum) in the manufacturing process to assembly and bonding, the manual assembly and handling phases can be almost fully eliminated. In this paper recent development to manufacture freeform and flexible electronics components and systems using printing and hybrid integration processes is presented. Production examples of hybrid integration will be presented for 1) LED display, 2) a large area roll-to-roll processed LED luminaire, 3) over-moulded optical touch panel and 4) over-moulded OLED subassembly.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126570270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Slowing of Moore's law signals the beginning of smart everything 摩尔定律的放缓标志着万物智能的开始
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-09-01 DOI: 10.1109/ESSCIRC.2014.6942013
S. Sutardja
{"title":"Slowing of Moore's law signals the beginning of smart everything","authors":"S. Sutardja","doi":"10.1109/ESSCIRC.2014.6942013","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942013","url":null,"abstract":"After more than four decades of semiconductor revolution led by CMOS technology, the ability to shrink transistors by 50% every 18 to 24 months is finally coming to an end. For years, the end of transistor scaling, otherwise known as the end of Moore's law, had been prematurely predicted. Case in point just as the industry thought that the fundamental optical wavelength limit would finally inhibit the progress of Moore's law, wet lithography came to the rescue; giving us 40nm and then 28nm logic process nodes. Now however, in order to get even smaller transistors, we are finding out we need to replace the age old planar bulk transistors with Finfet. The industry will also need to use more expensive and time consuming multi patterning techniques starting with double patterning at the 16nm node and quad patterning at 10nm and at 7nm; drastically increasing the mask cost. As a result, after taking into account the mask costs, we can no longer have the fantastic cost reductions of the past from device scaling. Therefore from an economic point of view, the beginning of the end of Moore's law is now upon us.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122423669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Terahertz electronics: The last frontier 太赫兹电子学:最后的前沿
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-09-01 DOI: 10.1109/ESSDERC.2014.6948750
T. Lee
{"title":"Terahertz electronics: The last frontier","authors":"T. Lee","doi":"10.1109/ESSDERC.2014.6948750","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948750","url":null,"abstract":"The terahertz gap is a roughly decade-wide spectral band geometrically centered at 1THz, for which neither conventional electronics nor room-temperature photonics is particularly well suited. This paper reviews applications that reside in the gap, mapped against the capabilities of various technologies. Lithographic scaling will deliver devices with adequate small-signal performance in the THz band, but the lack of efficient, high-power (watt-level) sources remains a significant impediment to further progress. The paper concludes with an enumeration of work still to be done, and some suggestions for how it might be done, including a recommendation not to overlook appropriately reconceived vacuum electronic devices.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116680543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of etch stop layer on negative bias illumination stress of amorphous Indium Gallium Zinc Oxide transistors 刻蚀停止层对非晶铟镓锌氧化物晶体管负偏置照明应力的影响
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-09-01 DOI: 10.1109/ESSDERC.2014.6948820
A. Bhoolokam, M. Nag, A. Chasin, S. Steudel, Jan Genoe, G. Gelinck, G. Groeseneken, P. Heremans
{"title":"Impact of etch stop layer on negative bias illumination stress of amorphous Indium Gallium Zinc Oxide transistors","authors":"A. Bhoolokam, M. Nag, A. Chasin, S. Steudel, Jan Genoe, G. Gelinck, G. Groeseneken, P. Heremans","doi":"10.1109/ESSDERC.2014.6948820","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948820","url":null,"abstract":"In this work we show that the negative bias illumination stress (NBIS) of amorphous Indium Gallium Zinc Oxide (a-IGZO) transistors with an etch stop layer (ESL) deposited by physical vapor deposition (PVD) is substantially better than the NBIS of devices where the ESL layer is deposited by plasma enhanced chemical vapor deposition (PECVD). Both devices show similar transistor characteristics and bias stress in the dark but under NBIS conditions at 425 nm, PVD ESL based transistors show much less threshold voltage shift. The reduction in deep defects due to passivation by PVD layer is responsible for improved performance under NBIS.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129897074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
How chips helped discover the Higgs boson at CERN 芯片是如何帮助欧洲核子研究中心发现希格斯玻色子的
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-09-01 DOI: 10.1109/ESSCIRC.2014.6942014
W. Snoeys
{"title":"How chips helped discover the Higgs boson at CERN","authors":"W. Snoeys","doi":"10.1109/ESSCIRC.2014.6942014","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2014.6942014","url":null,"abstract":"Integrated circuits and devices revolutionized particle physics experiments, and have been a cornerstone in the recent discovery of the Higgs boson by the ATLAS and CMS experiments at the Large Hadron Collider at CERN. Particles are accelerated and brought into collision at specific interaction points. Detectors are giant cameras, about 40 m long by 20 m in diameter, constructed around these interaction points to take pictures of collision products as they fly away from the collision point. They contain millions of channels, often implemented as reverse biased silicon pin diode arrays covering areas of up to 200 m2 in the center of the experiment, generating a small (~1fC) electric charge upon particle traversals. Integrated circuits provide the readout, and accept collision rates of about 40 MHz with on-line selection of potentially interesting events before data storage. Power consumption directly impacts the measurement quality as it governs the amount of material present in the detector. Radiation tolerance has to exceed space requirements by orders of magnitude. The presence of tens of thousands of chips in a single system requires special attention to uniformity, robustness and redundancy.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134128701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automotive electronics: Application & technology megatrends 汽车电子:应用与技术大趋势
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-09-01 DOI: 10.1109/ESSDERC.2014.6948749
F. Marchio, B. Vittorelli, Roberto Colombo
{"title":"Automotive electronics: Application & technology megatrends","authors":"F. Marchio, B. Vittorelli, Roberto Colombo","doi":"10.1109/ESSDERC.2014.6948749","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948749","url":null,"abstract":"The complexity of the requirements for automotive applications is increasing at an astonishing pace. Concepts from other domains are being introduced in order to address these demands. For example we now need to cover fault tolerant and failsafe systems. The functional safety of systems, products and processes increases with every day and with every new development and we must maintain a grasp of the risks during every phase: from the first concept through development and from operation through shutdown. With the increased connectivity and complexity there are serious security challenges for the design of automotive hardware/software architectures due to attacks. Virtualization is now being made available in automotive embedded environments providing developers with the ultimate open platform: the ability to run any flavor of operating system in any combination, creating an unprecedented flexibility for deployment and usage. With the immense processing power that is being unlocked with multi-processor systems we are now able to address complex issues such as a complete inspection of the vehicle's environment. In this paper we will discuss the challenges of implementing a safe, secure, complex driver assistance system that paves the way towards autonomous driving.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132004731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Bionic skins using flexible organic devices 使用柔性有机装置的仿生皮肤
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-03-13 DOI: 10.1109/MEMSYS.2014.6765575
T. Someya
{"title":"Bionic skins using flexible organic devices","authors":"T. Someya","doi":"10.1109/MEMSYS.2014.6765575","DOIUrl":"https://doi.org/10.1109/MEMSYS.2014.6765575","url":null,"abstract":"We will report our recent research activities to apply ultraflexible and stretchable electronic systems for biomedical applications. First, we describe recent progress of ultraflexible organic devices such as organic thin film transistors (OTFTs), organic photovoltaic cells (OPVs), and organic light-emitting diodes (OLEDs) that are manufactured on ultrathin plastic film with the thickness of 1 μm. Then these ultraflexible organic devices were utilized to fabricate and other wearable and implantable electronic systems including 64-channel surface electromyogram measurement sheets.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123354548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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