F. Andrieu, M. Cassé, E. Baylac, P. Perreau, O. Nier, D. Rideau, R. Berthelon, F. Pourchon, A. Pofelski, B. D. Salvo, C. Gallon, V. Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, V. Barral, R. Ranica, N. Planes, W. Schwarzenbach, E. Richard, E. Josse, O. Weber, F. Arnaud, M. Vinet, O. Faynot, M. Haond
{"title":"双通道(sSOI衬底，SiGe沟道)平面FDSOI mosfet的应变和布局管理","authors":"F. Andrieu, M. Cassé, E. Baylac, P. Perreau, O. Nier, D. Rideau, R. Berthelon, F. Pourchon, A. Pofelski, B. D. Salvo, C. Gallon, V. Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, V. Barral, R. Ranica, N. Planes, W. Schwarzenbach, E. Richard, E. Josse, O. Weber, F. Arnaud, M. Vinet, O. Faynot, M. Haond","doi":"10.1109/ESSDERC.2014.6948769","DOIUrl":null,"url":null,"abstract":"We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs\",\"authors\":\"F. Andrieu, M. Cassé, E. Baylac, P. Perreau, O. Nier, D. Rideau, R. Berthelon, F. Pourchon, A. Pofelski, B. D. Salvo, C. Gallon, V. Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, V. Barral, R. Ranica, N. Planes, W. Schwarzenbach, E. Richard, E. Josse, O. Weber, F. Arnaud, M. Vinet, O. Faynot, M. Haond\",\"doi\":\"10.1109/ESSDERC.2014.6948769\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.\",\"PeriodicalId\":262652,\"journal\":{\"name\":\"2014 44th European Solid State Device Research Conference (ESSDERC)\",\"volume\":\"66 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 44th European Solid State Device Research Conference (ESSDERC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2014.6948769\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 44th European Solid State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2014.6948769","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs
We fabricated Fully-Depleted (FD) nMOSFETs on strain-SOI substrates (sSOI), exceeding regular FDSOI devices by +20% in nMOS ON-state current (ION) and +18% in SRAM read current. For pMOSFETs on sSOI, the integration of Si0.57Ge0.43 by the Ge-enrichment technique (in so-called sSGOI) is the solution to reach the performance of Si0.78Ge0.22 channels built on SOI (SGOI) in terms of short channel hole mobility and ION. We analyse the layout effects in sSOI/sSGOI transistors, ring oscillators (ROs) and SRAMs for different Ge amounts and strains and report for the first time the carrier mobility in sSOI/sSGOI vs. the active length (Lac). Through a layout optimization, a high uniaxial strain can be created, boosting the carrier mobility in both sSOI/sSGOI by 10/20% and ensuring the scalability of the planar FDSOI architecture for the 10nm node.
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