A. Redaelli, L. Laurin, S. Lavizzari, C. Cupeta, G. Servalli, A. Benvenuti
{"title":"High Ion/Ioff ratio BJT selector for 32 cell string Resistive RAM arrays","authors":"A. Redaelli, L. Laurin, S. Lavizzari, C. Cupeta, G. Servalli, A. Benvenuti","doi":"10.1109/ESSDERC.2014.6948804","DOIUrl":null,"url":null,"abstract":"A compact low leakage selector is needed for any resistive RAM arrays to enable the correct memory operation. In particular Phase Change Memories are demanding in terms of trade off between low leakage and driving current capability due to the Joule-heating-based programming mechanism. This work addresses a full integration path for optimizing bipolar junction transistor (BJT) to realize long string of base-emitter junctions up to 32, enabling the reduction of the base straps overhead thus further reducing the effective array size in respect to conventional approach. The optimization between the base resistance value and base-emitter leakage is not trivial and it has been performed by working on junction position and process thermal budget mainly by TCAD. Experimental validation has been provided on a 45 nm PCM vehicle, demonstrating the feasibility of the proposed approach.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 44th European Solid State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2014.6948804","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A compact low leakage selector is needed for any resistive RAM arrays to enable the correct memory operation. In particular Phase Change Memories are demanding in terms of trade off between low leakage and driving current capability due to the Joule-heating-based programming mechanism. This work addresses a full integration path for optimizing bipolar junction transistor (BJT) to realize long string of base-emitter junctions up to 32, enabling the reduction of the base straps overhead thus further reducing the effective array size in respect to conventional approach. The optimization between the base resistance value and base-emitter leakage is not trivial and it has been performed by working on junction position and process thermal budget mainly by TCAD. Experimental validation has been provided on a 45 nm PCM vehicle, demonstrating the feasibility of the proposed approach.