发布求助
文献互助 智能选刊 最新文献

2014 44th European Solid State Device Research Conference (ESSDERC)最新文献

筛选
英文 中文
Energy efficiency and conversion in 1D and 2D electronics 一维和二维电子学的能源效率和转换
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948751
E. Pop, C. English, F. Xiong, Feifei Lian, A. Serov, Zuanyi Li, S. Islam, V. Dorgan
{"title":"Energy efficiency and conversion in 1D and 2D electronics","authors":"E. Pop, C. English, F. Xiong, Feifei Lian, A. Serov, Zuanyi Li, S. Islam, V. Dorgan","doi":"10.1109/ESSDERC.2014.6948751","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948751","url":null,"abstract":"We review our recent studies at the intersection of energy, nanomaterials and nanoelectronics. Through careful high-field studies of two-dimensional (2D) devices based on graphene and MoS2, we have uncovered details regarding their physical properties and band structure. We have investigated thermoelectric effects in graphene transistors and phase-change memory (PCM) elements for low-power electronics. We find that low-power transistors and memory could be enhanced by built-in thermoelectric effects which are particularly pronounced at nanometer length scales. We have also examined heat flow in composites based on one-dimensional (1D) carbon nanotubes, and uncovered both the lower (diffusive) and upper (ballistic) limits of heat flow in 1D and 2D nanomaterials. Our results suggest fundamental limits and new applications that could be achieved through the co-design of geometry, interfaces, and selection of 1D and 2D nanomaterials.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122935012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of discrete dopants on an ultra-scaled FinFET using quantum transport simulations 用量子输运模拟研究离散掺杂对超尺度FinFET的影响
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948831
R. Ferreiro, Antonio Martinez, M. Aldegunde, J. Barker
{"title":"Impact of discrete dopants on an ultra-scaled FinFET using quantum transport simulations","authors":"R. Ferreiro, Antonio Martinez, M. Aldegunde, J. Barker","doi":"10.1109/ESSDERC.2014.6948831","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948831","url":null,"abstract":"In this paper we study the effect of random discrete dopants in the source/drain on the performance of a 6.6 nm channel length silicon FinFET. Due to the small dimensions of the FinFET, a quantum transport formalism based on the Non-equilibrium Greens Functions has been deployed. The transfer characteristics for several devices, which differ in location and number of dopants have been simulated. Our calculations demonstrated that discrete dopants modify the effective channel length and the height of the source/drain barrier, consequently changing the channel control of the charge. As a consequence, there is a strong effect on the variability of the off-current, sub-threshold slope and threshold voltage. Finally, we have calculated the mean and standard deviation of these parameters to quantify their variability.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116523540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Temperature dependence of threshold voltage fluctuations in CMOS transistors incorporating halo implant 含光环植入的CMOS晶体管阈值电压波动的温度依赖性
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948848
H. Edwards, Niu Jin, F. Hou, L. J. Choi, T. Krakowski, K. Joardar
{"title":"Temperature dependence of threshold voltage fluctuations in CMOS transistors incorporating halo implant","authors":"H. Edwards, Niu Jin, F. Hou, L. J. Choi, T. Krakowski, K. Joardar","doi":"10.1109/ESSDERC.2014.6948848","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948848","url":null,"abstract":"We report a device physics theory and compact model that predicts the threshold voltage mismatch for CMOS transistors using the halo implant. This model is able to fit CMOS VT mismatch across temperature and device geometry, validating the underlying physical argument. A bias method is presented and shown to recover part of the matching degradation due to the halo implant.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134352549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Study of surface weak spots on SiC Schottky Diodes under specific operating regimes by Infrared Lock-in sensing 基于红外锁定传感的SiC肖特基二极管在特定工作条件下表面薄弱点的研究
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948841
J. Leon, X. Perpiñà, M. Vellvehí, X. Jordà, P. Godignon
{"title":"Study of surface weak spots on SiC Schottky Diodes under specific operating regimes by Infrared Lock-in sensing","authors":"J. Leon, X. Perpiñà, M. Vellvehí, X. Jordà, P. Godignon","doi":"10.1109/ESSDERC.2014.6948841","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948841","url":null,"abstract":"Several Silicon Carbide Schottky Barrier Diodes (SBDs) were inspected by Infrared Lock-In Thermography to study and determine the origin of structural weak spots resulting from their manufacturing and electro-thermal stressing tests. These spots are frequency modulated following three different approaches representative of their operating conditions and detected by their infrared emission, as they behave as hot spots. Such weak spots could have originated from barrier modification due to wire-bonding process, non-uniform active area resistance for bad metallization electrical contact, deep level traps creation due to high energy implantation in the edge termination, and internal crack propagation during thermal cycling.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133205911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low dark count rate and low timing jitter InGaAs/InP Single-Photon Avalanche Diode 低暗计数率和低时序抖动InGaAs/InP单光子雪崩二极管
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948763
A. Tosi, M. Sanzaro, Niccolo Calandri, A. Ruggeri, F. Acerbi
{"title":"Low dark count rate and low timing jitter InGaAs/InP Single-Photon Avalanche Diode","authors":"A. Tosi, M. Sanzaro, Niccolo Calandri, A. Ruggeri, F. Acerbi","doi":"10.1109/ESSDERC.2014.6948763","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948763","url":null,"abstract":"We describe the design and characterization of a new InGaAs/InP Single-Photon Avalanche Diode (SPAD) for single-photon detection at 1.55 μm with high detection efficiency, low noise and low timing jitter. The design and fabrication have been optimized to reduce the defects (responsible for dark counts and afterpulsing). Zinc diffusion is a key step and we optimized the profile, pattern and reactor parameters to achieve uniform sensitivity in the active area, low noise and low timing jitter. The active area diameter of the device here described is 25 μm and no floating guard rings are present. It is operated in gated mode, with passive quenching, for the characterization. The dark count rate is in the order of few kilo-counts per second at 225 K and 5 V of excess bias. The photon timing resolution, measured as the full-width at half maximum of the response to a 20 ps pulsed laser, is about 90 ps, with a clean exponential tail whose time constant is about 60 ps. The photon detection efficiency is about 30% at 1550 nm. These specifications make our InGaAs/InP SPAD a good candidate for advanced time-correlated singlephoton counting applications at wavelengths up to 1700 nm.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132282387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
PDMS-supported graphene transfer using intermediary polymer layers 使用中间聚合物层的pdms支持的石墨烯转移
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948822
S. Vaziri, A. Smith, G. Lupina, M. Lemme, M. Östling
{"title":"PDMS-supported graphene transfer using intermediary polymer layers","authors":"S. Vaziri, A. Smith, G. Lupina, M. Lemme, M. Östling","doi":"10.1109/ESSDERC.2014.6948822","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948822","url":null,"abstract":"We propose a graphene transfer method based on chemical vapor deposited (CVD) graphene grown on copper foils. This transfer method utilizes a combination of a silicone elastomer (PDMS) and different intermediate polymer layers depending on the process requirements. We use polystyrene and polystyrene/photoresist intermediary layers for dry and wet graphene release. PMMA intermediary layer is applied for bubbling-assisted graphene transfer. The elastomer layer serves as an excellent solid support for electrochemical graphene delamination. Graphene-based field effect transistors (GFETs) were fabricated and characterized using this process. Raman spectroscopy was used in order to verify a successful transfer.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"985 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133070308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Thermal characterization and modeling of ultra-thin silicon chips 超薄硅片的热表征与建模
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948844
M. Alshahed, Zili Yu, H. Rempp, H. Richter, C. Harendt, J. Burghartz
{"title":"Thermal characterization and modeling of ultra-thin silicon chips","authors":"M. Alshahed, Zili Yu, H. Rempp, H. Richter, C. Harendt, J. Burghartz","doi":"10.1109/ESSDERC.2014.6948844","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948844","url":null,"abstract":"Manufacturing ultra-thin chip is an emerging field in semiconductor technology that is driven by 3-D integrated circuits and flexible electronics. Unlike bulk silicon (Si) chips with thickness greater than 400 μm, the thermal management of ultra-thin Si chips with thickness smaller than 20 μm is challenging due to the increased lateral thermal resistance implying stringent cooling requirements. Therefore, a reasonable prediction of temperature gradients in such chips is necessary. In this work, a thermal chip is implemented in an ultra-thin 0.5 μm CMOS technology to be employed in surface steady-state and transient temperature measurement. Test chips are either packaged in a Pin Grid Array (PGA) ceramic package or attached to a flexible polyimide substrate. The experimental results show an on-chip temperature gradient of ~15 °C for a dissipated power of 0.4 W in the case of the PGA package and ~30 °C for the polyimide substrate. The time constants are ~50 s and ~ 1 s for the PGA and the polyimide packages respectively. The measurements are complemented by FEM simulations using ANSYS 14.5 workbench. In addition, a lumped-element thermal circuit model is developed and used for the surface temperature prediction, which is compared to measurement results.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115307748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Degradation of dc and pulsed characteristics of InAlN/GaN HEMTs under different proton fluences 不同质子效应下InAlN/GaN hemt直流和脉冲特性的退化
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948840
I. Rossetto, F. Rampazzo, S. Gerardin, M. Meneghini, M. Bagatin, A. Zanandrea, A. Paccagnella, G. Meneghesso, E. Zanoni, C. Dua, M. Forte-Poisson, R. Aubry, M. Oualli, S. Delage
{"title":"Degradation of dc and pulsed characteristics of InAlN/GaN HEMTs under different proton fluences","authors":"I. Rossetto, F. Rampazzo, S. Gerardin, M. Meneghini, M. Bagatin, A. Zanandrea, A. Paccagnella, G. Meneghesso, E. Zanoni, C. Dua, M. Forte-Poisson, R. Aubry, M. Oualli, S. Delage","doi":"10.1109/ESSDERC.2014.6948840","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948840","url":null,"abstract":"Displacement-damage induced degradation in InAlN/GaN structures is studied for different proton fluences, from 110<sup>14</sup> p/cm<sup>2</sup> to 410<sup>14</sup> p/cm<sup>2</sup>, at 3MeV. DC analysis reveals that devices experience a V<sub>TH</sub> positive shift and an increase of the R<sub>ON</sub>, following a linear trend with the proton radiation fluence, as a consequence of the creation of acceptor-like traps. Furthermore an increase of the diode gate current is noticed. Pulsed measurements indicate an increase of the so called “current collapse”, especially when a high gate drain voltage difference is applied, as a consequence of the performances variation in the dynamic max g<sub>m</sub>, V<sub>TH</sub> shift and R<sub>ON</sub>.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115834559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analog SiPM in planar CMOS technology 平面CMOS技术中的模拟SiPM
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948818
F. Villa, D. Bronzi, M. Vergani, Yu Zou, A. Ruggeri, F. Zappa, A. D. Mora
{"title":"Analog SiPM in planar CMOS technology","authors":"F. Villa, D. Bronzi, M. Vergani, Yu Zou, A. Ruggeri, F. Zappa, A. D. Mora","doi":"10.1109/ESSDERC.2014.6948818","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948818","url":null,"abstract":"Silicon Photomultipliers (SiPMs) are emerging single photon detectors used in many applications requiring large active area, photon number resolving capability and immunity to magnetic fields. We developed planar analog SiPMs in a reliable and cost-effective CMOS technology with a total photosensitive area of about 1×1 mm2. Three devices with different active areas, and fill-factor (21%, 58.3%, 73.7%), have been characterized. The maximum photon detection efficiency is in the near-UV and tops at 38% (fill-factor included), with a dark count rate of 125 kcps. Gain and crosstalk depend on the active area size and are comparable to those of commercial best-in-class custom-technology SiPMs. However our full CMOS processing enables advanced SiPM single-chip systems where transistors and further on chip electronics can be integrated together with the detectors.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116023472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
High performance high reliability AlN/GaN DHFET 高性能高可靠性AlN/GaN DHFET
2014 44th European Solid State Device Research Conference (ESSDERC) Pub Date : 2014-11-06 DOI: 10.1109/ESSDERC.2014.6948779
F. Medjdoub, E. Okada, Bertrand Grimbert, D. Ducatteau, Riccardo Silvestri, M. Meneghini, E. Zanoni, G. Meneghesso
{"title":"High performance high reliability AlN/GaN DHFET","authors":"F. Medjdoub, E. Okada, Bertrand Grimbert, D. Ducatteau, Riccardo Silvestri, M. Meneghini, E. Zanoni, G. Meneghesso","doi":"10.1109/ESSDERC.2014.6948779","DOIUrl":"https://doi.org/10.1109/ESSDERC.2014.6948779","url":null,"abstract":"We report on AlN/GaN double heterostructures for high frequency applications. 600 hours preliminary reliability assessment has been performed on these emerging RF devices, showing promising millimeter-wave 100 nm gate length GaN-on-Si device stability for the first time. A 150 nm AlN/GaN double heterostructure has been developed and evaluated on SiC substrate. State-of-the-art CW power-added-efficiencies (PAE) at 10 and 18 GHz have been achieved on ultrathin barrier (6 nm) GaN devices while operating at a drain bias exceeding 30 V.","PeriodicalId":262652,"journal":{"name":"2014 44th European Solid State Device Research Conference (ESSDERC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127180070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信