GaN virtual prototyping: From traps modeling to system-level cascode optimization

Abstract

The present paper focuses on the system-level optimization of GaN technology for high voltage applications. We will show that a key requirement for the future success of the GaN technology is the full system-optimization achieved by a simultaneous optimization of technology, packaging and applications. We will also show that Virtual Prototyping (VP) becomes, in GaN technology, a fundamental tool that allows not only to have a fundamental understanding of the device properties but more importantly it allows to strongly link device optimization, technology and system-level performance. In the present paper we will describe our view on the system-level optimization of high voltage GaN technology and present detailed simulations and comparison with experiments for both normally on isolated GaN transistors and cascoded GaN devices in real switching applications.