2006 64th Device Research Conference最新文献

{"title":"Effect of Poly-Si Gate Depletion on Tuning Range in MOS Varactors","authors":"J. Kulkarni, N. Bhat","doi":"10.1109/DRC.2006.305128","DOIUrl":"https://doi.org/10.1109/DRC.2006.305128","url":null,"abstract":"High quality and high tuning range on chip varactors are needed for implementation of VCOs in the standard CMOS technologies for RF applications. Varactors are implemented as a reverse biased diode or as a MOS capacitor operating in accumulation-depletion region [1]. The MOS varactors are preferred due to their superior tuning range compared to the diode [2]. The tuning range in MOS varactor is governed by oxide capacitance (Cox) and the minimum silicon capacitance in depletion (Cdep min). Since the gate oxide thickness dictates the maximum capacitance in a MOS capacitor structure, further improvement in the tuning range can be achieved, if the minimum capacitance is decreased further. To improve the varactor tuning range, Poly-Silicon depletion effect is exploited [3]. Poly-Silicon depletion effect arises due to low doping in the Poly-Si and formation of depletion region in Poly-Si region. This in turn reduces the effective gate capacitance Cox and consequently the drive current. Poly-Si depletion effect, which is generally avoided in order to design high performance CMOS transistors, is introduced intentionally by exposing the gate electrode of MOS varactor to appropriate implant steps [3] (Figure 1). The n-type doping concentration in the Poly-Si gate at the Poly-Si/oxide interface is intentionally decreased (N-). When the p-type silicon substrate is in accumulation mode (for VG < VFB), the gate Poly-Si is also in accumulation mode and hence the total gate capacitance is essentially Cox. However during the depletion mode (for VG > VFB), if the doping concentration near the Poly-Si/SiO2 interface is less than about IxIO19 cm-3, then the Poly-Si region near the SiO2 interface is also depleted. It can be viewed as an addition of another series capacitance, Cp01y (Figure 1). So effective capacitance is series combination of three capacitors. Thus adding the poly-depletion effect reduces Cminimum. The varactor structure is simulated in an optimized 100nm CMOS process flow [4]. The baseline CMOS process flow utilized disposable spacer technique [5] to optimize the varactor (VI) performance. Instead of p+ Poly-Si, the varactor structure use n-type Poly-Si gate and p-type substrate with p+ deep source/drain implants for making the contacts. The different varactor structures V2, V3 and V4 are realized by defining appropriate boolean operations on Poly-Si masks for NMOS (PMOS) deep source/drain implant and NMOS (PMOS) extension/halo implants as shown in table I [3]. The maximum improvement in the tuning range, with respect to the reference device, is observed to be 60 00 in varactor V4 as shown in figure 2. For measuring the Q factor, the admittance matrix is calculated. The conductance between gate and other electrode for various cases is as shown in figure 3. It is observed that there is no significant change in the conductance value. So quality factor is not degraded. Poly-Si gate in varactor V4, which gives maximum tuning range, is exposed to NMOS h","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132221400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SiC Nanocrystal Flash Memory Fabricated with Protein-mediated Assembly","authors":"Yueran Liu, S. Tang, Chuanbin Mao, S. Banerjee","doi":"10.1109/DRC.2006.305148","DOIUrl":"https://doi.org/10.1109/DRC.2006.305148","url":null,"abstract":"As a potential candidate of future flash memory, flash memory with nanocrystal floating gate is getting more and more attention because of its high program/erase speed, long retention time and good scaling ability [1, 2]. However, one most important challenge for flash memory with nanocrystal floating gate is the size and distribution control of the nanocrystal. Selfassembly of nanocrystals with traditional methods, such as chemical vapor deposition (CVD) [3], cannot get uniform size and distribution even with surface pre-treatments. This will cause the variation of electronic characteristics for final memory devices. Protein has been demonstrated to be a good template to organize the nanocrystals on SiO2 surface based on our previous work [4]. In this paper, we will present our studies about flash memory with SiC nanocrystal fabricated with protein-mediated assembly. P-MOS capacitors with SiC nanocrystal floating gate on SiO2 were fabricated on n-type Si (100) substrate. The schematic structure is shown in Fig. 1. After thermal oxidation for tunnel oxide, the wafer was immersed in PTS (phenyltriethoxysilane) solution in order to pretreat the surface. Next, the wafer was floated on the chaperonin protein solution with the oxide side down. The chemical environment of each chaperonin's central cavity was used to trap a nanocrystal. Once nanocrystals were trapped by the chaperonin template, the template was removed by annealing in 02 at 2000C. The density of nanocrystals up to 1012/cm2 has been demonstrated. The thicknesses of tunnel oxide and control oxide are 4nm and 12nm, respectively. A clear hysteresis with around 1.7 V flatband voltage shift can be observed from the high frequency capacitance-voltage (HFCV) characteristics (Fig 2), which is a clear effect of the charge stored the nanocrystals. The gate voltage is swept from inversion to accumulation to get forward HFCV and from accumulation back to inversion to get reverse HFCV. Fig 3 shows the memory programming and erasing speed characteristics with +8V and 1IOV pulse. After program and erase, 0.3 V flatband voltage shift can be observed even if the pulse width is shrunk to 1 00ls. Because of the deep well created by SiC nanocrystals, the flash memory shows very good retention characteristics at both room temperature and 85°C (Fig 4). After excess charge loss in the initial step, the charge loss rate is as small as 0.005/decade at 85°C and a memory window larger than 1V will be obtained after 10 years. In the endurance measurement, after up to 105 program/erase cycles with I1OV lOms pulse, the memory window does not show obvious closure. We have experimentally demonstrated the significant advantages of the SiC nanocrystal floating gate with long retention and good endurance characteristics.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114429167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"300GHz Transistor Performance in Production CMOS Technologies","authors":"B. Jagannathan, D. Chidambarrao, J. Pekarik","doi":"10.1109/DRC.2006.305055","DOIUrl":"https://doi.org/10.1109/DRC.2006.305055","url":null,"abstract":"CMOS technology scaling has resulted in a continuous improvement in RF performance of silicon MOSFETs. fT and fMAX in excess of 300GHz has been demonstrated in production CMOS nodes [1]. 400GHz fT for ultra-short channel MOSFET with LGATE of 10nm has also been reported [2]. CMOS based RF solutions are already mainstream for applications in the 1-10GHz regime and with the RF performance of these devices improving rapidly, CMOS technology has the potential to enable low-power mm-wave applications as well. This paper will review the design and performance of state-of-the-art RF MOSFETs. RF CMOS device design relies on leveraging digital FET design coupled with geometry optimization to maximize device performance. COnsidering a small signal device model with parasitic resistances, fT of the device can be expressed as, 1/2¿fT=Cin/gm+Cin/gm(rs +rd)gd+(rs+rd)Cgd. Even in FETs with LGATE ~ 25nm, the parasitic resistances and gd have a minimal impact on fT. If parasitic capacitances can be kept to a minimum then, fT=gm/2¿Cin. From this expression, it can be observed that in velocity saturated devices, fT ¿ 1/LGATE. This direct dependence on channel length has been the driving force for fT scaling in the FETs. in state-of-the CMOS nodes, gm also benefits from carrier mobility enhancement techniques. Tensile stress in the channel induced by nitride liners and \"stress-memorization\" has resulted in as much as 30% improvement of gm in nFETs [3,4].","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134123190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring Low Temperature Poly-Si for Low Cost and Low Power Sub-micron Digital Operation","authors":"Jing Li, A. Bansal, K. Roy","doi":"10.1109/DRC.2006.305118","DOIUrl":"https://doi.org/10.1109/DRC.2006.305118","url":null,"abstract":"In recent years, low power consumption at medium performance (10-1OOMHz) has become the primary design criteria for portable devices such as cellular phones, medical electronics etc. Fabrication of such digital circuits on flexible substrates will open plethora of applications integrating computational power in every walk of human life. Sub-micron silicon technologies are able to provide desired low-power and performance, however, fabrication requires large thermal budget making them unsuitable for flexible substrates. Flexible substrates limit the thermal budget to 500°C, inhibiting the fabrication of ultra-thin gate dielectrics. To reduce the fabrication costs, we explore amorphous (a) and low temperature polycrystalline (LTp) silicon thin-film transistors (TFTs) for digital circuits on flexible substrates. Conventionally, LTp-Si TFTs are used in active-matrix LCDs as pixel switching elements and integrated drivers because of their ease of fabrication on plastic substrates. Low thermal budget limits the grain size and gate dielectric thickness (To,) scaling. Small grain size reduces the carrier mobility because of traps at the grain boundaries (GBs) and non-scaled To, degrades the I-V characteristics, further degrading the performance. To improve the performance, grain size can be increased using Metal Induced Lateral Crystallization, Solid Phase Crystallization etc., however, it increases thermal budget and fabrication costs. Another option would be to scale the gate lengths of LTp-Si down to average grain size. However, reducing the gate lengths will require scaled gate dielectric increasing the thermal budget. We propose a methodology to optimize LTp-Si TFTs to improve performance while keeping short-channel-effect (SCE) under control along with low thermal budgetfor digital VLSI circuits onflexible substrates. For TFTs, first a-Si is deposited and then crystallized to increase the grain size. LTp-Si has average grain size of few hundred nanometers. LTp-Si TFTs can have longitudinal and latitudinal grain boundaries. With process control and careful layout, GBs in a channel can be restricted to longitudinal only. In p-Si, mobility is affected by the carrier trapping at the GB regions (Fig. 1). The carrier transport in good quality grains is similar to that of crystalline silicon (c-Si). The effective mobility can be given by [1]","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125320241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Negative Capacitance in Organic Light-Emitting Diodes: Implications for Display Applications","authors":"L. Pingree, M. Russell, T. Marks, M. Hersam","doi":"10.1109/DRC.2006.305159","DOIUrl":"https://doi.org/10.1109/DRC.2006.305159","url":null,"abstract":"","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125587070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A High-intensity Nano-aperture Vertical-Cavity Surface-Emitting Laser With Controlled Polarization","authors":"Zhilong Rao, J. Matteo, L. Hesselink, J. Harris","doi":"10.1109/DRC.2006.305150","DOIUrl":"https://doi.org/10.1109/DRC.2006.305150","url":null,"abstract":"near-field optical data storage. Also, data transfer rates canbegreatly increased iftheVCSELsareapplied inparallel arrays[11. Previous workonnanoaperture VCSELsutilize conventional circular apertures whichsuffer fromlowpoweroutput through thenanoaperture whentheaperture size becomes muchsmaller thanonewavelength[23]. We propose toapply aunique C-shaped nano-aperture (C-aperture) ontoVCSELs.Fromsimulation, theC-aperture showsthree orders of magnitude higher powertransmission efficiency thanaconventional square orcircular aperture producing thesame near-field spotsize[41. We report herearecord-high near-field intensity of15.4mW/[tm2 achieved fromournanoaperture VCSELwitha70nmC-aperture. Ourtop-emitting VCSELsaredesigned tooperate around 970nmandconsist of9.5pairs ofp-type distributed Bragg reflectors (DBR),three strain-compensated InGaAs/GaAsP quantumwellsand38.5pairs ofn-DBRs.The reflectivity ofthetopmirror isenhanced witha150nmthick Aucoating. We insert ahalf-wavelength thick SiO2 filmbetween theAucoating andthetopDBR pairs toenhance thetransmission through thenano-aperture. We use wetoxidation ofAlGaAstoobtain a2.8pim-diameter oxide aperture forcurrent andmodeconfinement. Thenanoapertures areetched through theAucoating using aFocused IonBeam(FIB). Thetransmission oflight through theC-aperture ispolarization-dependent. Forthematched polarization, theCaperture produces awell-confined near-field spotwithhighintensity. However, fortheorthogonal mismatched polarization, theresulted near-field spotispoorly confined andtheintensity istwoorders ofmagnitude lower. Since VCSELsnormally havetwodegenerate orthogonal polarization states, weneedtocontrol thepolarization ofthe VCSELsinorder toapply theC-aperture ontheVCSELs.We openfour50*1500nm slits surrounding a70nmCaperture intheAu coating using FIBtocontrol thepolarization. Sincethetransmission oflight polarized perpendicular totheslit ismuchhigher thanthatoflight polarized parallel totheslit, thepolarization ofthe VCSELsiseffectively controlled tobeparallel totheslit duetolower loss inthis direction. Toidentify howmuchnetpowercomesoutoftheC-aperture, weblock thelight transmitted through theslits by depositing 150nmthick Pttofill theslits using electron-beam assisted chemical vapordeposition onaFIB/SEM dual-beam system. Pthasreflectivity of73%at1ptm, compared withreflectivity of95%forAu.Sothepolarization selectivity bytheslits ismaintained after theslits arefilled withPt.We measured thepolarization-resolved power","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125905772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of TUNNETT Diode as Terahertz Device and Its Applications","authors":"J. Nishizawa, T. Kurabayashi, P. Płotka, H. Makabe","doi":"10.1109/DRC.2006.305053","DOIUrl":"https://doi.org/10.1109/DRC.2006.305053","url":null,"abstract":"Recently, terahertz (THz) spectroscopy with imaging has attracted attention for application in the fields of medicine, pharmacy, and biology [1]. A compact THz light source by electron device with highly stable of frequency and output power is desired. We have fabricated TUNNETT with continuous-wave fundamental-mode oscillation in the frequency range up to 700 GHz at room-temperature operation. TUNNETT, a transit-time diodes with tunnel injection of electron shown in Figure 1 was invented in 1958 [2]. The first operating device ofTUNNETT was demonstrated by Nishizawa in 1968 [3], and fundamental-mode 100 GHz devices generating 100 mW ofRF power were achieved by Eisele et al [4].","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129426464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Numerical simulation of giant magnetoresistance resonant tunneling diodes","authors":"C. Ertler, J. Fabian","doi":"10.1109/DRC.2006.305075","DOIUrl":"https://doi.org/10.1109/DRC.2006.305075","url":null,"abstract":"tunneling diodes Christian Ertler and Jaroslav Fabian Institute for Theoretical Physics, University of Regensburg, 93040 Regensburg, Germany email: Semiconductor spintronics [1] has benefited greatly from the discovery of novel magnetic semiconductors such as GaMnAs. Indeed, this material has boosted prospects for field effect, bipolar, as well as tunneling spintronic devices at temperatures greater than 100 K. What is still missing are specific device proposals for this material to be incorporated in novel or conventional device structures. At present the most explored spintronic devices appear to be resonant tunnel diodes [2] that use dilute magnetic semiconductors like ZnMnSe as active magnetic materials. These diodes, which are used for spin filtering, are projected to lead to applications in magnetic sensing and, perhaps more prominently, in reprogrammable logic.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124455070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Impact of Strained Engineering for 65nm FUSI CMOSFETs","authors":"Chieh-Ming Lai, Yean-Kuen Fang, W. Yeh, Chien-Ting Lin","doi":"10.1109/DRC.2006.305123","DOIUrl":"https://doi.org/10.1109/DRC.2006.305123","url":null,"abstract":"Chieh-Ming Lail, Yean-Kuen Fang', Wen-Kuan Yeh2, Chien-Ting Lin 1. Institute of Microelectronics, National Cheng Kung University, Taiwan. 2. Department of Electrical Engineering, National University of Kaohsiung, Taiwan. No. 1 University Road, Tainan, TAIWAN, 70101, Tel: 886-6-2080398, FAX: +886-6-2345482 e-mail: ykfangAeembox.ee.ncku.edu.tw As the devices geometry is scaled down continually, some issues such as the boron penetration, poly gate depletion and low carrier mobility become more critical and serious. Metal gate is an efficient approach to eliminate the boron penetration and poly gate depletion [1], and fully silicided (FUSI) is a promising metal gate candidate due to the simplified processing as well as the tunable work function [2]. On the other hand, the high stress contact etch stop layer (CESL) has been used extensively to promote channel carrier mobility in conventional devices [3]. However, very few studies inspected the impact of high tensile stress CESL (TS CESL) on FUSI devices performance yet. In this work, we investigated the device driving capacity, leakages, low frequency noise (LF noise) and C-V characteristics for 65nm Ni-FUSI CMOSFETs with and without the TS CESL. Devices were fabricated using a modified standard CMOS process. After S/D Cobalt salicidation, the first TS CESL (700A) was deposited (Fig. 1(a): control device). After the inter layer dielectric oxide was deposited, FUSI CMP planarization was adopted to remove the I't TS CESL down to polysilicon gate. In this work, Ni-silicide has been used for the FUSI technology because of lower thermal budget and better properties [4]. Finally, the Ni-FUSI gate electrode was formed after RTP (Fig. 1(b)). In order to inspect the impact of high tensile stress in Ni-FUSI devices, some Ni-FUSI devices were deposited by TS CESL (700A) (Fig. 1(c)). Figure 2 shows the ID-VD curves for nMOSFETs with IVG-VTI=lV, it is found that devices with Ni-FUSI gate possess higher driving capacity than control devices do, which is due presumably to the better gate control under the same VG-VT; therefore, larger channel charges will be induced in channel region, lowering the channel resistance. Besides for these Ni-FUSI devices, the driving capacity can be also enhanced by a TS CESL. It implied that the TS CESL is an efficient method to improve driving capacity in Ni-FUSI devices. Fig. 3 shows that Ni-FUSI devices with TS CESL possess the highest Gm MAX. In Fig. 4, because of the positive shift of flatband voltage, the Ni-FUSI devices possess higher threshold voltage (VT) and better subthreshold swing especially for devices with TS CESL. In comparison with control device, the best noise performance was found in Ni-FUSI devices without TS CESL, as shown in Fig. 5. In Fig. 6, the Ni-FUSI devices without TS CESL possess lower junction leakages than the control devices does. For devices with Ni-FUSI gate, lower junction leakages was found, which is due presumably to the smoother band bending in Si","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122559093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inversion-mode Operation of Thermally-oxidized Modulation-doped Silicon Nanowire Field Effect Devices","authors":"Yanfeng Wang, T. Ho, S. Dilts, K. Lew, Bangzhi Liu, S. Mohney, J. Redwing, T. Mayer","doi":"10.1109/DRC.2006.305172","DOIUrl":"https://doi.org/10.1109/DRC.2006.305172","url":null,"abstract":"There has been considerable interest in bottom-up integration of semiconductor nanowires for their application in future logic, memory, and sensor circuits.1,2 Uniformly-doped pand n-type silicon nanowires (SiNWs) of varying carrier density have been synthesized and used to fabricate SiNW field effect transistors (FETs).3'4'5'6 Moreover, dry oxidation of as-grown SiNWs has been shown to suppress the large hysteresis observed in the subthreshold characteristics of unpassivated back-gated SiNW FETs and facilitate fabrication of top-gated SiNW FETs using the SiO2 shell as the gate dielectric.6 However, these SiNW FETs operate by modulation of the Schottky-barrier at the source/drain (S/D) contacts or by depletion of the doped channel, which gives rise to low on-state currents and on-off ratio. In this talk, we will present the results of topgated FETs fabricated using thermally-oxidized SiNWs with axially-modulated n+-p--n+ doping that operate by inversion of the p-channel and show a dramatic improvement in device properties as compared to uniformly-doped SiNW FETs.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122474809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}