{"title":"300GHz Transistor Performance in Production CMOS Technologies","authors":"B. Jagannathan, D. Chidambarrao, J. Pekarik","doi":"10.1109/DRC.2006.305055","DOIUrl":null,"url":null,"abstract":"CMOS technology scaling has resulted in a continuous improvement in RF performance of silicon MOSFETs. fT and fMAX in excess of 300GHz has been demonstrated in production CMOS nodes [1]. 400GHz fT for ultra-short channel MOSFET with LGATE of 10nm has also been reported [2]. CMOS based RF solutions are already mainstream for applications in the 1-10GHz regime and with the RF performance of these devices improving rapidly, CMOS technology has the potential to enable low-power mm-wave applications as well. This paper will review the design and performance of state-of-the-art RF MOSFETs. RF CMOS device design relies on leveraging digital FET design coupled with geometry optimization to maximize device performance. COnsidering a small signal device model with parasitic resistances, fT of the device can be expressed as, 1/2¿fT=Cin/gm+Cin/gm(rs +rd)gd+(rs+rd)Cgd. Even in FETs with LGATE ~ 25nm, the parasitic resistances and gd have a minimal impact on fT. If parasitic capacitances can be kept to a minimum then, fT=gm/2¿Cin. From this expression, it can be observed that in velocity saturated devices, fT ¿ 1/LGATE. This direct dependence on channel length has been the driving force for fT scaling in the FETs. in state-of-the CMOS nodes, gm also benefits from carrier mobility enhancement techniques. Tensile stress in the channel induced by nitride liners and \"stress-memorization\" has resulted in as much as 30% improvement of gm in nFETs [3,4].","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 64th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2006.305055","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
CMOS technology scaling has resulted in a continuous improvement in RF performance of silicon MOSFETs. fT and fMAX in excess of 300GHz has been demonstrated in production CMOS nodes [1]. 400GHz fT for ultra-short channel MOSFET with LGATE of 10nm has also been reported [2]. CMOS based RF solutions are already mainstream for applications in the 1-10GHz regime and with the RF performance of these devices improving rapidly, CMOS technology has the potential to enable low-power mm-wave applications as well. This paper will review the design and performance of state-of-the-art RF MOSFETs. RF CMOS device design relies on leveraging digital FET design coupled with geometry optimization to maximize device performance. COnsidering a small signal device model with parasitic resistances, fT of the device can be expressed as, 1/2¿fT=Cin/gm+Cin/gm(rs +rd)gd+(rs+rd)Cgd. Even in FETs with LGATE ~ 25nm, the parasitic resistances and gd have a minimal impact on fT. If parasitic capacitances can be kept to a minimum then, fT=gm/2¿Cin. From this expression, it can be observed that in velocity saturated devices, fT ¿ 1/LGATE. This direct dependence on channel length has been the driving force for fT scaling in the FETs. in state-of-the CMOS nodes, gm also benefits from carrier mobility enhancement techniques. Tensile stress in the channel induced by nitride liners and "stress-memorization" has resulted in as much as 30% improvement of gm in nFETs [3,4].