2006 64th Device Research Conference最新文献

{"title":"Ultra-Low Threshold Lasing in a Quantum Dot Microdisk Cavity","authors":"S. Gotzinger, Z. Xie, G. Solomon","doi":"10.1109/CLEO.2007.4452488","DOIUrl":"https://doi.org/10.1109/CLEO.2007.4452488","url":null,"abstract":"We describe microdisk lasers exhibiting submicrowatt CW lasing thresholds from a small number of QD emitters. Changes in the cavity linewidth, second-order correlation measurements, and output emission versus input pumping are used to verify lasing.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134220213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of High-Power Vertical GaN-Based Light-Emitting Diodes with Selective Nickel Electroplating and Patterned Laser Lift-Off Techniques","authors":"Shui-Jinn Wang, Shiue-lung Chen, K. Uang, Wei-Chi Lee, Tron-min Chen, B. Liou, Su-Hua Yang","doi":"10.1109/DRC.2006.305156","DOIUrl":"https://doi.org/10.1109/DRC.2006.305156","url":null,"abstract":"A novel process for fabricating high-power Vertical-structure Metallic substrate GaN-based light-emitting diodes (VM-LEDs) employing selective nickel electroplating and patterned laser lift-off (LLO) techniques was proposed. Advantages including the avoidance of metal-cutting process, easy in die size definition through laser spot control, and simplification of fabrication processes (i.e., fewer masks as well as less effort in wire bonding) were demonstrated. As compared to regular lateral-structure LEDs, the VM-LEDs experimentally show having an increase in light output power (Lop) (i.e., ¿Lop/Lop) by 293.4% at 350 mA with a decrease in forward voltage from 3.73 V down to 3.32 V.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"48 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124400134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Silicon on Insulator CMOS with Hybrid Crystal Orientation Using Double Wafer Bonding","authors":"K. Chan, M. Yang, L. Shi, A. Kumar, J. Ott, J. Patel, R. Schultz, H. Kry, Y. Zhang, E. Sikorski, W. Graham, B. To, S. Medd, D. Canaperi, J. Newbury, C. Scerbo, R. Meyer, C. D'Emic, M. Ieong","doi":"10.1109/DRC.2006.305110","DOIUrl":"https://doi.org/10.1109/DRC.2006.305110","url":null,"abstract":"Carrier transport depends critically on MOSFET channel orientation, with electron mobility highest on the conventional Si (100) surface while hole mobility is more than 2x enhanced on the Si (110) surface [1]. CMOS on substrates composed of multiple surface orientations have been demonstratednFETs on the (100) surface orientation and pFETs on the (110) surface orientation -yielding pFET drive current enhancement of 30% at 45nm channel length [2]. However, in most of the previous publications on Hybrid Orientation Technology (HOT), nFETs were fabricated on silicon-on-insulator (SOI), but pFETs were bulk-like. The implementation of this HOT technology is therefore limited by the design changes during technology transfer. Furthermore, it is known that CMOS on SOI provides higher performance than conventional bulk device due the elimination of area junction capacitance (Cja), the lack of a reverse body effect in stacked circuits and the slightly forward biased SOI body under the nominal operating voltage range. In this paper, we present a novel SOI CMOS structure on hybrid orientation substrates through double wafer bonding.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117170330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Organic complementary circuits using solution deposited active semiconductors","authors":"B. Yoo, D. Basu, Taeho Jung, D. Fine, B. Jones, A. Facchetti, M. Wasielewski, T. Marks, K. Dimmler, A. Dodabalapur","doi":"10.1109/DRC.2006.305061","DOIUrl":"https://doi.org/10.1109/DRC.2006.305061","url":null,"abstract":"","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117192215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low work-function TaN-metal gate with Gadolinium oxide buffer layer on Hf-based dielectrics","authors":"G. Thareja, S. Rhee, H. Wen, Rusty Harris, P. Majhi, B. Lee, Jack C. Lee","doi":"10.1109/DRC.2006.305134","DOIUrl":"https://doi.org/10.1109/DRC.2006.305134","url":null,"abstract":"Reduction in effective work function (EWF) of mid gap-TaN metal gate electrode with Gadolinium (Gd2O3) buffer layer in Hafnium based high-K gate stack has been demonstrated. EWF of 4.2eV was achieved for TaN with a bi-layer arrangement of Gd2O3/HfSiOx dielectric. By using Gd-Si co-sputtered layer on HfO2, a reduction in EWF to NMOS compatible EWF of 4.05eV was obtained. NMOSFETs with improved output current, transconductance, and channel electron mobility highlight the approach of using Gadolinium in the gate stack.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127498089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhancement and Depletion-mode GaAs N-MOSFETs with stacked HfO2/Y2O3 gate dielectric","authors":"F. Zhu, S. Koveshnikov, I. Ok, H. Kim, V. Tokranov, M. Yakimov, S. Oktyabrsky, W. Tsai, J. Lee","doi":"10.1109/DRC.2006.305129","DOIUrl":"https://doi.org/10.1109/DRC.2006.305129","url":null,"abstract":"","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127529762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physical Mechanisms Limiting the Channel Mobility in 4H-SiC MOSFETs","authors":"K. Matocha, V. Tilak, S. Balaji, S. Arthur, R. Rao, J. Tucker","doi":"10.1109/DRC.2006.305143","DOIUrl":"https://doi.org/10.1109/DRC.2006.305143","url":null,"abstract":"SiC lateral MOSFETs were fabricated on an epitaxially-grown p-well on an n-type 4HSiC substrate. Source and drain regions were implanted with Nitrogen, and a body contact region was co-implanted with Aluminum and Carbon. Wafers were capped with graphite and implants were activated for 30 minutes at 1650°C. After sacrificial oxidation, the 80 nm gate oxide was grown at 1250°C in N20 followed by NO oxidation at 1175°C. A liftoff process was used to deposit Nickel for Ohmic contacts to n-type and p-type regions. The Molybdenum gate metal was deposited and patterned and then the Ohmic contacts were annealed at 1050°C for 3 minutes. Annular long-channel MOSFETs (Lch=100 pm) and MOS-gated Hall structures were fabricated and characterized as a function of temperature.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126098585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reduction of Gate Leakage Current of Ultra thin Silicon Oxynitride via RTP-Induced Phonon-Energy-Coupling Enhancement","authors":"Pang-leen Ong, C. Samantaray, Zhi Chen","doi":"10.1109/DRC.2006.305127","DOIUrl":"https://doi.org/10.1109/DRC.2006.305127","url":null,"abstract":"Aggressive scaling of ultra-thin SiO2 and SiOXNy gate dielectric has caused a number of problems, such as high gate leakage current and reliability degradation. Recently, we reported phonon-energy-coupling enhancement (PECE) effect, i.e. the Si-O bonds in SiO2 are strengthened due to energy coupling from Si-O rocking mode to the Si-Si TO mode using rapid thermal processing (RTP) directly on the oxide [1,2]. The energy coupling is further enhanced after the oxide is annealed in deuterium. The gate leakage current was reduced by five orders of magnitude, which is equivalent to that of HfO2 and HfSiON reported elsewhere [3,4]. Fig. 1 shows the FTIR spectra of the vibration modes of the SiO2/Si sample, where the Si-O TO rocking mode are enhanced significantly upon RTP anneal in N2 for a short period of time. The enhancement of the Si-O bonds can be visualized from the schematic illustration shown in Fig. 2. However, the current mainstream gate dielectric used in industry is SiOxNy. Thus, it is very important to study the PECE effect in SiOXNy, because Si-O and Si-Si bonds also exist in SiOXNy. In this work, we fabricated ultra-thin SiOxNy MOS capacitors that exhibit 4 orders magnitude reduction of tunneling leakage current after using RTP induced PECE effect. MOS capacitors were fabricated on 2-inch p-type (100)-oriented wafers (1-10 Q-cm) via process steps shown in Table 1. XPS measurements were performed on one of the control samples to identify the chemical bonding in the as-grown oxynitride film. Fig. 3 shows the deconvolution of N Is spectra using Gaussian curve fitting with four peaks observed at binding energies 397.9, 400.6, 401.9, and 403.6 eV corresponding to NSi3, NSi2O, NSiO2, and NO3 bondings respectively [5]. Fig. 4 shows the 0 Is spectrum with a distinct peak at 531.6 eV. Fig. 5 shows the deconvolution of the Si 2p spectra with peaks of Si, Si-N, and Si-O, at binding energies 99.4, 102.85, and 103.95 eV respectively. From these XPS spectra, nitrogen concentration was calculated to be approximately 4.7 00 atomic composition. We can then approximate the dielectric constant to be 4.5 [6] and apply it to the ellipsometry measurements (M-44 spectroscopic ellipsometer) to obtain the Equivalent Oxide Thickness (EOT). The EOT of the oxynitride film is approximately 21 A as determined by the above method. It should be noted that the thickness measurements on all the samples before and after RTP treatment showed no thickness variations. High-frequency CV measurements at 1 MHz for the pMOS capacitors are shown in Fig. 6. Flat band voltages of -0.9 V, equivalent to the work function difference between the Al gate and the p-Si, were extracted from the CV measurements for the control and RTP-treated samples. This indicates that there is no significant amount of fixed charges in these samples. The oxynitride film thickness ranging from 20.8 to 21.5 A was extracted from the strong accumulation capacitance of the CV measurements using dielectric consta","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"2 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123698366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Growth and uses of metal/semiconductor heterostructures","authors":"A. Gossard","doi":"10.1109/DRC.2006.305068","DOIUrl":"https://doi.org/10.1109/DRC.2006.305068","url":null,"abstract":"Dozens of metallic compounds exist that potentially can be grown epitaxially on and in semiconductors. The rare-earth group Ill-V metallic compounds are particularly noteworthy. We illustrate the growth and uses of such compounds by studies of the molecular beam epitaxy of erbium-based Ill-V metallic compounds with simple rock-salt crystal structure on and in Ill-V semiconductors. 1) All-epitaxial metal/semiconductor microwave detector diodes, 2) time-domain Terahertz sources and detectors based on embedded metal nanoparticles, 3) thermo-electric power generators based on embedded nanoparticles, and 4) tandem solar cells coupled by monolayers of metallic epitaxial nanoparticles are all showing record-breaking performance. It is apparent that the epitaxial metal/semiconductor heterostructure is joining the semiconductor/semiconductor heterostructure as a key element in enhanced-performance electronic and optoelectronic devices.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125428243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Proposal of Broadband High-Q Monolithic Active Inductors by Using Resonant Tunneling Diodes","authors":"M. Suhara, H. Horie, T. Okumura","doi":"10.1109/DRC.2006.305117","DOIUrl":"https://doi.org/10.1109/DRC.2006.305117","url":null,"abstract":"In this paper, we propose and analyze a novel broadband high-Q active inductor on the basis of integration with resonant tunneling diodes (RTDs) revealing negative differential resistance (NDR). The proposed implementation of the active inductor is shown in Fig. 1. The basic concept is to realize the active inductor by using immittance transformation of an external capacitance Co with an broadband active gyrator which is formed by two resonant tunneling diodes (RTDs) and a FET. Alternative approaches to realize active inductors have been reported only based on GaAs FETs[1], HBTs[2] and CMOS transistors[3], however, to our knowledge, the RTD-based active gyrator has never been proposed so far. Moreover, the RTD-based broadband active inductor has a possibility to exhibit larger Q-values than others even when typical practical values of parasitic component are considered.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115188824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}