2006 64th Device Research Conference最新文献

{"title":"30-nm-gate AlGaN/GaN MIS-HFETs with 180 GHz fT","authors":"M. Higashiwaki, T. Matsui, T. Mimura","doi":"10.1109/DRC.2006.305161","DOIUrl":"https://doi.org/10.1109/DRC.2006.305161","url":null,"abstract":"AlGaN/GaN heterostructure field-effect transistors (HFETs) are excellent candidates for high power and high frequency applications operating in the millimeter-wave frequency range. Therefore, it is important to clarify how fast GaN HFETs can operate, because this will be key information to judge the frequency limit of GaN HFET applications. We recently reported AlGaN/GaN HFETs with a current-gain cutoff frequency (fT) of 163 GHz, which is a record for GaN transistors [1]. The high fT was achieved with our novel approach using high-Al-composition and extremely thin AlGaN barriers, SiN gate-insulating and passivation layers deposited by catalytic chemical vapor deposition (Cat-CVD), and 60-nm-long T-gates, which makes it possible to maintain a high aspect ratio for sub-0.1 -pim gates and suppress the short-channel effect. To enhance high-frequency characteristics, for the present work, we further decreased the gate length (LG) and fabricated 30-nm-gate AlGaN/GaN HFETs. The decrease in LG successfully resulted in the enhancement offT, which reached a new record of 180 GHz. Figure 1 shows a schematic cross section of the SiN(2 nm)/Alo.4Gao.6N(8 nm)/AlN(1.3 nm)/GaN(1500 nm) MIS-HFET. The structure was grown on a sapphire substrate by plasma-assisted molecular-beam epitaxy (PAMBE), and all of the epitaxial layers were nominally undoped. The patterning processes except for the gate finger were done by photolithography with a contact aligner. Device isolation was performed by mesa dry etching with C12/BCl3/Ar mixture gas. Source and drain ohmic contacts were formed by rapid thermal annealing of Ti/Al/Ni/Au at 820°C. The specific contact resistance was 3 x 10-6 Qcm2. Cat-CVD at 300°C was used to deposit a 2-nm-thick SiN film on the device. The SiN film worked not only as a passivation film but also as a gate-insulating layer. 30-nm-long T-shaped gates were defined by electron-beam (EB) lithography with a triple-layer resist, and gate metal with Ti/Pt/Au was deposited and lifted off. Finally, contact pad metal for probing with Ti/Au was deposited and lifted off. The source-drain spacing was 2 pim, and the gate width was 50x2 pim. Four-point van der Pauw Hall patterns were fabricated on the same wafer during the device processing. After SiN deposition, a mobility of 827 cm2/Vs, an electron density (Ns) of 2.07x1013 cm-2, and a sheet resistance (Rsh) of 364 Q/square were obtained for the HFET structure from the Hall effect measurement. The large Ns and low Rsh in spite of the thin AlGaN barrier were attributed to the Cat-CVD SiN passivation [2]. Figure 2 shows DC current-voltage (I-V) curves for the 30-nm-gate HFETs. The devices had a good pinch-off characteristic. The maximum drain current density (IDs) reached 1.49 A/mm for a gate bias of +1 V. Figure 3 shows the transfer characteristics for a drain bias of 2 V. The peak extrinsic transconductance (gm) was 402 mS/mm. Figure 4 shows the gate leakage current characteristics. The two-terminal reverse breakdow","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116580354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrical detection of spin accumulation in ferromagnet-semiconductor devices","authors":"X. Lou, C. Adelmann, M. Furis, S. Crooker, C. Palmstrom, P. Crowell","doi":"10.1109/DRC.2006.305070","DOIUrl":"https://doi.org/10.1109/DRC.2006.305070","url":null,"abstract":"insemiconductors isfarless advanced. We focus hereontheimportant caseofan interface between aferromagnetic metal (iron) andGaAs.Although isolated successes havebeenreported previously2, ithasbeenextremely difficult toisolate small signals fromthebackground contributions that exist duetothepresence offerromagnetic electrodes. We address this particular problem byusing an approach inwhichwedetect asignal that issensitive onlytothedephasing ofspins byprecession ina transverse magnetic field. We showthat theaccumulation ofspin-polarized electrons ataforward-biased Schottky tunnel barrier between Feandn-GaAscanbedetected electrically. Thespinaccumulation, whichhasbeenobserved previously usingoptical techniques,3'4 leads toanadditional voltage dropacross thebarrier thatis suppressed byasmall transverse magnetic field. Thiseffect, whichisduetothedepolarization ofspins in thetransverse field, isequivalent totheHanleeffect observed inoptical pumping experiments. The experiment5 iscarried outonlateral devices withtwoepitaxial Fe/GaAsSchottky tunnel barriers at opposite endsofann-doped (n= 3.6x1016 cm-3) GaAschannel. Additional contacts along thechannel are usedtomeasure thevoltages across thesource anddrain independently. Thelateral geometry allows usto carry outtransport andKerrmicroscopy measurements onthesamedevice. Asverified bytheKerr measurements,4 spins caneither beinjected atthesource contact oraccumulated atthedrain duetothe spin-dependent reflectivity oftheFe/GaAs interface. A magnetic field isapplied perpendicular tothe plane, sothatthemagnetizations oftheelectrodes remain fixed throughout theelectrical transport measurements. Thefield-dependence ofthevoltage across thereverse-biased source contact isnearly featureless overthefield range oftheexperiment. Incontrast, apronounced peakatzerofield isobserved inthevoltage measured across theforward-biased drain contact. Thisasymmetry withrespect tothe current direction isobserved inevery device overawidechannel doping range andisconsistent witha density ofstates argument basedontunnelling. We modelthefield dependence ofthevoltage by considering spinprecession, drift, diffusion, andrelaxation. Theapproach issimilar tothat used previously formetals, except that inthis casespins aregenerated anddetected atasingle ferromagnetic contact. Withtheexception oftheamplitude, all parameters required tofit thevoltage peakatzerofield areobtained fromindependent measurements. Athightemperatures (T> 30K),thewidth ofthepeakis determined predominantly bythespin lifetime. Inthis temperature range, themagnetic field dependence of theKerrrotation canbefitwiththesameparameters usedformodelling thevoltage peak, providing compelling support fortheinterpretation ofthetransport data. Thedemonstration ofaHanle effect intransport isasignificant step. Inthecasereported here, wehave usedonlyasingle electrode, whichfunctions asbotha\"source\" anda\"detector.\" Ourcurrent workis focusing onthenon-local geometry inwhichthespin polariza","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122448305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Extraction of Accumulation Mobility from C-V Characteristics of Pentacene MIS Structures","authors":"Keum-dong Jung, C. Lee, Dong-Wook Park, Byung-Gook Park, Hyungcheol Shin, J. Lee","doi":"10.1109/DRC.2006.305157","DOIUrl":"https://doi.org/10.1109/DRC.2006.305157","url":null,"abstract":"A novel method for extracting accumulation mobility of pentacene thin films has been proposed. To obtain the mobility, the sheet resistance and the accumulation charge of the film under negative gate bias are obtained from the capacitance-voltage(C-V) characteristics of the pentacene MIS structures. The value of the extracted mobility is 24% lower than that determined from the I-V characteristics ofOFET by conventional method [1]. Besides the attention paid to the mobility as a key performance factor in organic electronics, the mobility extraction method itself has been studied widely. Most of the methods using I-V characteristics require an accurate IV equation such as the silicon long-channel MOSFET model, but establishing a general OFET I-V equation has been a difficult problem. Therefore, to extract more reliable mobility, a novel mobility extraction method using C-V characteristics of pentacene MIS structure is described in this paper. Fig. 1 shows the cross-sectional view and top view of the fabricated devices. An n+-Si wafer is used as a gate electrode, and 35 nm-thick oxide is used as a gate insulator. Dilute PMMA is spin-coated on the SiO2 for the surface treatment. Finally, pentacene and gold are evaporated sequentially through shadow masks. The width W of the peripheral region is controlled by the shadow mask from 15 ptm to 95 ptm. C-V characteristics are measured in air with 14P4284A LCR meter with the frequency of 100 Hz -1 MHz and the gate voltage of-O0 V -10 V. In Fig. 2, the value of measured capacitance(C101) of the device is separated into three different capacitances: the insulator capacitance(C1), pentacene-gold overlapping capacitance(C2), and the peripheral region capacitance(Cp). Ci is directly measured from MIM capacitor, and C0, and Cp are indirectly obtained using the relation of C0,= C101 C, and C,= Ct1tC, C-C. Fig. 3 and Fig. 4 show the separation of Ct,t(W=75 rim) with different gate bias and measuring frequency, respectively. To extract the accumulation mobility pcac from pac= 1 IPhQA at a specific gate voltage, e.g., VG= -10 V, the sheet resistance Psh and the total accumulation charge per unit area QA at VG= -10 V should be known. First, QA of 716.22 nC/cm2 at VG = -10 V is directly obtained from the integration of C0, curve [2] as shown in Fig. 5. The flat band voltage VFB in the integration is determined from 11C0V2 curve to be -1.08 V. Next, to obtain Psh from the peripheral region capacitance CP, R-C network model in Fig. 6 is adopted to describe CP versus frequency behavior assuming uniform resistance R along the whole peripheral region and negligible resistance in the n+-Si gate and the contact. By the analogy with the small-signal gate resistance model of silicon MOSFETs [3], Cp versus frequency relation is given as","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114425436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"AlGaN/GaN Field-Effect Surface Acoustic Wave Filters with >40-dB Isolation for Monolithic Integration with HEMTs","authors":"N. Shigekawa, K. Nishimura, T. Suemitsu, H. Yokoyama, K. Hohkawa","doi":"10.1109/DRC.2006.305135","DOIUrl":"https://doi.org/10.1109/DRC.2006.305135","url":null,"abstract":"Microwave monolithic integrated circuits (MMICs) equipped with high-Q passive devices are likely to play an essential role in future wireless systems. Although surface acoustic waves (SAWs) have been widely used for realizing high-Q passive devices, monolithic integration of conventional insulator-based SAW devices and electron devices is not practical. Noting that group-IH nitrides are a promising material for such integration due to their semiconducting properties and large piezoelectricity, we previously fabricated SAW filters on GaN layers on (0001) sapphire substrates [1, 2]. In this paper, we report on characteristics of SAW filters with interdigital transducers (IDTs) composed of ohmic and Schottky contacts and those of HETs on AlGaN/GaN heterostructures, and discuss the possibility ofmonolithically integrating SAW and electron devices.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129502354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mobility in Back-Gate/Double-Gate Undoped Thin Silicon Channel Transistors","authors":"Setu Mohta, U. Avci, Arvind Kumar, S. Tiwari","doi":"10.1109/DRC.2006.305107","DOIUrl":"https://doi.org/10.1109/DRC.2006.305107","url":null,"abstract":"Arvind Kumar*, Setu Mohta, Uygar E. Avci+, Arvind Kumar4 and Sandip Tiwari School of Electrical and Computer Engineering, Cornell University. Ithaca, NY +Components Research Lab, Intel Corporation, Hillsboro OR, #IBM Research Center, Yorktown Heights, NY Email*: ak226(cornell.edu The important operational regions in back-gate/two-gate geometries [1-3] are: (a) where only one of the interface has carriers and (b) where both interfaces have carriers whose interactions are related to the silicon thickness. In scaled nchannel back-gate/two-gate structures, a large voltage at the back interface applied to obtain a high threshold voltage can also result in a two-carrier interaction where the back-interface has holes while the front interface has electrons. We demonstrate through experimental measurements the effective mobility behavior in back-gate transistors that utilize undoped thin silicon channel, thin back/front oxides and independently driven two gates device structure different from that of SOI transistors. We show that when conducting charge is at one interface, even with accumulation charge at the other interface (holes, e.g. at the back interface), a universal mobility relationship still holds as long as the sheet charge approximation is valid (silicon thickness > 10 nm). Absence of dopants and use of back potential results in a different effective field and mobility relationship compared to bulk and SOI structures. When electron charge is at both interfaces, the mobility degrades below the single interface low effective field limit. This work is the first report summarizing the universal relationship extending into accumulation-inversion limit for the interfaces, i.e., a wide bias range over which these devices are likely to be utilized. Measurements are performed on two-gate structures where following patterning of the back-gate, bonding and exfoliation is utilized to flip the structure and to form the front gate geometries [1]. The bonding interface is below the back-gate and the structure largely indistinguishable from a conventional CMOS transistor except for the presence of back-gate. Split C-V measurements are employed on large (100im x 100im) and smaller n-channel transistors. Front and back gates employ n+-doped polysilicon, and the thin silicon channel (47.5 nm) is obtained from exfoliation and selfstopping polishing from a 1 Q.cm p-type substrate. The effective mobility is extracted from conductance and 1 MHz","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114874063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Field-effect transistors and photodetectors based on solution-synthesized nanowires","authors":"Amol Singh, A. Khandelwal, X. Li, H. Xing, Masaru Kuno, D. Jena","doi":"10.1109/DRC.2006.305121","DOIUrl":"https://doi.org/10.1109/DRC.2006.305121","url":null,"abstract":"submitted to DRC 2006 Field-effect transistors and photodetectors based on solutionsynthesized nanowires A. Singh, A. Khandelwal, X. Li, H. Xing, M. Kuno, D. Jena University of Notre Dame, Notre Dame, IN 46556 Phone: 574 631 8835, Fax: 574 631 4393, email: djenagnd.edu Various semiconductor nanostructures, including nanotubes and nanowires have been grown and studied recently. The primary growth technique has been chemical vapor deposition (CVD)-based, such as the rather popular vaporliquid-solid (VLS) technique. [1] Growth techniques utilizing solution-based synthesis, on the other hand, have a number of advantages over the CVD technique such as low cost, scaling of production, ability to passivate the semiconductor surface chemically during growth, and the ease of transfer to any substrate. One such synthetic method is the solution-liquid-solid (SLS) technique, which has been used by various groups to produce colloidal quantum dots or nanocrystals.[2] Rudimentary photodetectors have been demonstrated using closed-packed \"solids\" of the SLS-grown nanocrystals. Though photon absorption and electron-hole pair generation in nanocrystals is efficient, the extraction of carriers is difficult, involving hopping transport between the dots before being collected by the electrodes. In this work, we demonstrate photodetectors based on CdSe nanowire networks, or \"quantum-wire solids\". Nanowires allow band-transport along their axes, therefore potentially offering a drastic improvement over nanocrystals for the efficient collection of optically generated carriers. To evaluate the transport properties of the nanowires, we have fabricated field-effect transistors using both single nanowires and networks of nanowires as channels on SiO2/Si substrates with back gates. For single nanowire FETs, focused ion beam has been employed to define Pt source-drain contacts. Typical nanowires diameters are 10nms, and lengths vary from 1-10 microns. For multiple nanowire channels, we have used ac dielectrophoretic alignment for precise placement of the nanowires between the source-drain contacts (Figure 1, right).[3] The nanowires FETs thus fabricated require a negative gate bias for pinch-off indicating that the wires are n-type, and drain-source current on/off ratios of 105 are observed for FETs with dense nanowires network channels, as opposed to -10 for single nanowires FETs (Figure 2, right). The temperature-dependence of the source-drain current (Fig 3, left) indicates that the charge transport is dominated by thermally generated carriers in the dark. Metal-semiconductor-metal photodetector devices are then fabricated using conventional optical lithography and metal deposition. The photodetectors are found to have very low dark currents (10 nA at 5 V), indicating very few free carriers in the nanowires at room temperature. The spectroscopic photoresponse of these photodetectors is measured using a xenon lamp coupled with a monochromator, and a lock-in amplifier in a p","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126495355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"III-Nitride Field-Effect Transistors with Capacitively-Coupled Contacts","authors":"G. Simin, Z. Yang, A. Koudymov, V. Adivarahan, J. Yang, M. Khan","doi":"10.1109/DRC.2006.305139","DOIUrl":"https://doi.org/10.1109/DRC.2006.305139","url":null,"abstract":"We demonstrate novel wide bandgap AlGaN/GaN heterostructure field-effect transistor design using capacitively-coupled electrodes (C3HFET). The source, gate and drain of C3HFET have capacitive coupling with the 2D-channel. Both Schottky and insulated gate (C3MOSHFET) device implementations have been realized. The devices do not require annealed ohmic contacts and can be fabricated using gate alignment-free technology. Besides obvious advantages in the fabrication technology, the C3HFETs and C3MOSHFETs have low effective RF contact resistance (below 0.5 Qmm) and are capable of handling much higher RF powers when used as RF control devices, such as power modulators, switches, attenuators etc. To the best of our knowledge this is first report of this type of wide bandgap high-power RF devices. To date nearly all the III-N high frequency electronic devices are based on 2D electron gas (2DEG) channel at the AlGaN-GaN heterointerface with high-temperature annealed source-drain ohmic contacts. The annealing temperatures (typically over 850 C) degrade AlGaN-GaN heterojunction, generate trapping centers, and may significantly reduce the device reliability. There exists a broad class of RF control devices, which operation does not require the DC bias. These are RF switches, attenuators, modulators, power limiters etc. For this device types we explore a new design approach using capacitive coupling between the metal electrodes and the high-density 2DEG at the AlGaN/GaN interface. Novel C3HFET consists of three metal electrodes, source, gate and drain, deposited on top of AlGaNGaN structure. The 25 nm thick A1025Ga075N barrier layer was grown by MOCVD over 1.5 pim thick undoped GaN buffer layer on SiC substrate. The C3MOSHFET has an additional 10 nm thick SiO2 layer under the metal electrodes. No annealing was used in device fabrication. The length of the source and drain electrodes, L= 5 ptm; the gate length LG=1 ptm. The source-drain spacing is LDs=5jm. Total device width W= 2 x 125 ptm. High-frequency characteristics of C3devices were measured using HP 851 OC network analyzer. Above the contact cut-off frequency of around 1 GHz, the insertion loss is the same or lower than that of a regular HFET or MOSHFET with annealed contacts. The effective contact resistance extracted from the S-parameters was below 0.5 Q-mm. The power-handling capability of novel C3 transistors was characterized at 10 GHz. The most significant large-signal distortions in RF control devices manifest themselves as an increase in the subthreshold currents due to channel potential modulation; normally, this increase in the sub-threshold current impose the most critical limitation on the maximum operating RF powers. As a result, the typical maximum operating (switching) RF powers do not exceed 1W for GaAs devices and around 20 W for the AlGaN/GaN based HFETs. We have found that for the novel AlGaN/GaN C3 HFETs and C3MOSHFETs the maximum RF powers were around 10 times higher than those of H","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Speed Characterization of Organic Thin Film Transistors","authors":"D. Basu, Liang Wang, L. Dunn, A. Dodabalapur, M. Heeney, I. McCulloch","doi":"10.1109/DRC.2006.305066","DOIUrl":"https://doi.org/10.1109/DRC.2006.305066","url":null,"abstract":"We have developed an electronic method to characterize the drift velocity and mobility of charge carriers in organic thin film transistors. The measurement is based on the movement of a packet of carriers injected into the channel. Drift mobilities obtained are greater than 1 cm2/Vs. These results can lead to the development of a class of circuits that can be operated in the megahertz range. This technique can also be used to explore trap states and therefore obtain a comprehensive understanding of charge transport in these materials. This experiment is the first of its kind to be performed on an organic transistor. Organic semiconductors are endowed with qualities such as easy processibility and variety of materials. However organic circuit applications are hindered by low speeds of operation. This is due to the fact that majority of the carriers are trapped in localized states resulting in low field-effect mobilities. However, existence of fast carriers in the channel of a pentacene transistor has been demonstrated by Dunn et. al. by exciting the transistor with a step voltage[ 1]. Drift mobilities of 0.18 cm2/Vs have been obtained for devices with field effect mobilities of 0.07 cm2/Vs. The impulse voltage method is an extension of the step voltage technique which can be used to measure the drift velocity under varying bias conditions. The schematic of the experiment is shown in figure 1. To study transport using the impulse method, the transistor is switched on and allowed to settle in a conducting state. This is followed by the superposition of a small perturbation, a 5 V impulse with a width (FWHM) of 15 nsec, at the source of the transistor, which is otherwise at 0 V (figure 2). Consequently a packet of charge carrier is injected into the channel. Simulations results shown in figure 3 indicate that the drift component of the injected carrier current exceeds its displacement counterpart. The diffusion component can also be neglected for these small timescales of operations. By restricting the drain bias to low voltages it can be safely assumed that the electric field is uniform inside the channel. The transit time can, therefore, be related to the drift mobility as t = L2/_ VDS. Once the carrier flux arrives at the drain, a bias-t is used to divert the transient current into a 500 Q resistor. The voltage across the resistor is therefore a measure of the current generated by the pulse. The shape of the current pulse for Vg = -90 at varying drain voltages is shown in figure 2. By subtracting the parasitic RC delays in the experimental setup, the true transit-time of current pulse can be extracted. This yields a mobility of 1.5 (+0.45, -0.2) cm2/Vs, which is -10 times higher than the FET mobility. Poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophenes) (pBTTT) was used for this study because of its high field effect mobilities [2]. Linear region mobility of 0. 12 cm2/Vs was obtained at VGS of -100 V. The experimental and simulated I-V ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133986055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology","authors":"Jae-Man Yoon, Kang-yoon Lee, Seung-bae Park, Seong-goo Kim, H. Seo, Young-woong Son, Bong-soo Kim, Hyun-Woo Chung, Choong-ho Lee, Wonshik Lee, Dong-chan Kim, Donggun Park, Wonshik Lee, B. Ryu","doi":"10.1109/DRC.2006.305083","DOIUrl":"https://doi.org/10.1109/DRC.2006.305083","url":null,"abstract":"for 4F2 DRAM Cell Array with sub 40 nm Technology Jae-Man Yoon, Kangyoon Lee, Seung-Bae Park, Seong-Goo Kim, Hyoung-Won Seo, Young-Woong Son, Bong-Soo Kim, Hyun-Woo Chung, Choong-Ho Lee*, Won-Sok Lee* *, Dong-Chan Kim* * *, Donggun Park*, Wonshik Lee and Byung-Il Ryu ATD Team, Device Research Team*, CAEP*, PD Team***, Semiconductor R&D Division, Samsung Electronics Co., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do, 449-711, Korea Tel) 82-31-209-4741, Fax) 82-31-209-3274, E-mail)","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131707947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rugged UHF 4H-SiC BJTs with Record 22.8 W/mm Power Density and 8.3 dB Gain","authors":"F. Zhao, I. Wurfl, K. Torvik, Johnson Chiu, M. Mallinger, J. Torvik, B. Zeghbroeck","doi":"10.1109/DRC.2006.305163","DOIUrl":"https://doi.org/10.1109/DRC.2006.305163","url":null,"abstract":"Feng Zhaol, Ivan-Perez Wurfll, Kristoffer Torvikl, John Chiu2, Mike Mallinger2, John Torvikl, and Bart Van Zeghbroeck\" 3 'Advanced Power Technology Colorado, Advanced Power Technology Inc., Boulder, CO, 80301, USA 2Advanced Power Technology RF, Advanced Power Technology Inc., Santa Clara, CA, 95051, USA 3Department of Electrical and computer Engineering, University of Colorado, Boulder, CO 80309, USA Phone: (303)442-4250, fax: (303)442-4251, email: fzhaogadvancedpower.com","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132972002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}