Mobility in Back-Gate/Double-Gate Undoped Thin Silicon Channel Transistors

Abstract

Arvind Kumar*, Setu Mohta, Uygar E. Avci+, Arvind Kumar4 and Sandip Tiwari School of Electrical and Computer Engineering, Cornell University. Ithaca, NY +Components Research Lab, Intel Corporation, Hillsboro OR, #IBM Research Center, Yorktown Heights, NY Email*: ak226(cornell.edu The important operational regions in back-gate/two-gate geometries [1-3] are: (a) where only one of the interface has carriers and (b) where both interfaces have carriers whose interactions are related to the silicon thickness. In scaled nchannel back-gate/two-gate structures, a large voltage at the back interface applied to obtain a high threshold voltage can also result in a two-carrier interaction where the back-interface has holes while the front interface has electrons. We demonstrate through experimental measurements the effective mobility behavior in back-gate transistors that utilize undoped thin silicon channel, thin back/front oxides and independently driven two gates device structure different from that of SOI transistors. We show that when conducting charge is at one interface, even with accumulation charge at the other interface (holes, e.g. at the back interface), a universal mobility relationship still holds as long as the sheet charge approximation is valid (silicon thickness > 10 nm). Absence of dopants and use of back potential results in a different effective field and mobility relationship compared to bulk and SOI structures. When electron charge is at both interfaces, the mobility degrades below the single interface low effective field limit. This work is the first report summarizing the universal relationship extending into accumulation-inversion limit for the interfaces, i.e., a wide bias range over which these devices are likely to be utilized. Measurements are performed on two-gate structures where following patterning of the back-gate, bonding and exfoliation is utilized to flip the structure and to form the front gate geometries [1]. The bonding interface is below the back-gate and the structure largely indistinguishable from a conventional CMOS transistor except for the presence of back-gate. Split C-V measurements are employed on large (100im x 100im) and smaller n-channel transistors. Front and back gates employ n+-doped polysilicon, and the thin silicon channel (47.5 nm) is obtained from exfoliation and selfstopping polishing from a 1 Q.cm p-type substrate. The effective mobility is extracted from conductance and 1 MHz