A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology

Jae-Man Yoon, Kang-yoon Lee, Seung-bae Park, Seong-goo Kim, H. Seo, Young-woong Son, Bong-soo Kim, Hyun-Woo Chung, Choong-ho Lee, Wonshik Lee, Dong-chan Kim, Donggun Park, Wonshik Lee, B. Ryu
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引用次数: 13

Abstract

for 4F2 DRAM Cell Array with sub 40 nm Technology Jae-Man Yoon, Kangyoon Lee, Seung-Bae Park, Seong-Goo Kim, Hyoung-Won Seo, Young-Woong Son, Bong-Soo Kim, Hyun-Woo Chung, Choong-Ho Lee*, Won-Sok Lee* *, Dong-Chan Kim* * *, Donggun Park*, Wonshik Lee and Byung-Il Ryu ATD Team, Device Research Team*, CAEP*, PD Team***, Semiconductor R&D Division, Samsung Electronics Co., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do, 449-711, Korea Tel) 82-31-209-4741, Fax) 82-31-209-3274, E-mail)
基于亚40nm技术的4F2 DRAM单元阵列低漏电流VPT集成
采用 40 纳米以下技术的 4F2 DRAM 单元阵列 Jae-Man Yoon, Kangyoon Lee, Seung-Bae Park, Seong-Goo Kim, Hyoung-Won Seo, Young-Woong Son, Bong-Soo Kim, Hyun-Woo Chung, Choong-Ho Lee*、Won-Sok Lee* *, Dong-Chan Kim* * *, Donggun Park*, Wonshik Lee 和 Byung-Il Ryu 三星电子公司半导体研发部 ATD 团队、器件研究团队*、CAEP*、PD 团队****。,San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do, 449-711, Korea Tel) 82-31-209-4741, Fax) 82-31-209-3274, E-mail)
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