2006 64th Device Research Conference最新文献_第10页

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305126

A. Gokirmak

{"title":"Accumulated Body MOSFET","authors":"A. Gokirmak","doi":"10.1109/DRC.2006.305126","DOIUrl":"https://doi.org/10.1109/DRC.2006.305126","url":null,"abstract":"Multi-gate MOSFET structures have been investigated in recent years for increased electrostatic control of the channel potential and electrostatic threshold voltage tunability. Multi-gate transistors typically have two parallel gates straddling the device body [1]. We have integrated additional side-gates to planar nMOSFETs fabricated on bulk Si platform using Si3N4 shallow trench isolation (STI) with 19 nm Si3N4 side-gate insulator, and 4 nm thermally grown SiO2 top-gate insulator (Fig. 1). The side-gate surrounds the active area such as a guard ring, and the top-gate is independently controlled [2]. The side-gates of the device are used to accumulate the side-interfaces with application of a negative bias, while the top-gate is used for transistor operation as in a conventional FET. Accumulation of the holes at the periphery results in significant reduction in defect assisted recombination current from drain to substrate at the side interfaces (Fig.2), thus increased defect tolerance and reliability for strained Si technologies [3]. As the device width is reduced, the side interfaces draw near, countering the depletion effects. This results in accumulation of the device body for narrow channel devices (Fig. Id). The narrow channel devices exhibit distinctly different characteristics depending on the channel width and the amount the side-gates are recessed below the level of active area (Fig. ib), resembling tri-gate FET [3], as opposed to being at the same level (Fig.Ic). The accumulation of the side-interfaces suppresses the peripheral Ids leakage along the Si-STI interfaces and eliminate the need for edge implants [5] while resulting in excellent characteristics, such as an lo,/Ioff > 6 x 1010 for aW x L = 0.6 pim x 0.3 pim device (Fig. 3,4). As the width of the device is reduced close to the depletion depth (Wd) in the channel region, the source, drain junction depletion are reduced, as well as depletion region under the gate. This results in suppression of leakage currents due to punch through and drain induced barrier lowering (DIBL) for short channel devices as a function Of VSid, (Fig. 5-8). The physical gate length of this device is estimated to be 69 nm from SEM and effective width (Weff) is estimated to be 150 nm from its C-V characteristics, indicating significant side-gate recess given that W,= 79 nm. Maximum drive current of this device exceeds 1.6 mA/ Im Weff. The effective mobility (4etff) calculated for a Weff= 23 nm, Leff 140 nm device is below 100 cm2 V-s (Fig. 9), however, the maximum saturation transconductance, gm = 0.74 mANV.im, result in an estimated electron saturation velocity of 8.6 x 106 cm/s [6]. At these device dimensions DIBL is suppressed below 10 mVNV. Planar accumulated body FETs with Weff < 10 nm exhibit extreme Vt response to VSid, (Fig. 10). Vt can be tuned from 1 V to 4 V within the -0.5 V < VSid, < -2 V range with sensitivity, Y = V/6Vside > -2.1 V/V in the -0.5 > Vside > -1 V regime. The threshold voltage ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114463721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

High-Speed Photodiodes and Related Devices 高速光电二极管及相关器件

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305051

T. Ishibashi, Hiroshi Ito

引用次数: 0

Comparing High Mobility InGaAs FETs with Si and GOI Devices 比较高迁移率InGaAs fet与Si和GOI器件

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305130

C. Liao, H. Kao, A. Chin, D. Yu, M. Li, C. Zhu, S. Mcalister

引用次数: 7

A field-programmable antifuse memory for RFID on plastic 一种用于塑料RFID的现场可编程防熔断存储器

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305063

B. Mattis, V. Subramanian

引用次数: 2

A Low-Cost Strained Silicon SRAM Technology with Reduced Contact Resistance 低接触电阻的低成本应变硅SRAM技术

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305174

I. Polishchuk, S. Levy, R. Kapre, O. Pohland, K. Ramkumar, Nirav R. Shah, S. Thompson

引用次数: 0

Device, Circuit and System Dimensions of 3-D Integration 3-D集成的设备、电路和系统尺寸

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305106

S. Tiwari, Christianto C. Liu, S. Kim

引用次数: 0

Spintronics - from materials through devices to circuits - 自旋电子学——从材料到器件再到电路

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305094

H. Ohno

引用次数: 3

Reduction of 1/f Noise in Carbon Nanotube Devices 碳纳米管器件中1/f噪声的降低

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305182

Y. Lin, J. Appenzeller, C. Tsuei, Z. Chen, P. Avouris

{"title":"Reduction of 1/f Noise in Carbon Nanotube Devices","authors":"Y. Lin, J. Appenzeller, C. Tsuei, Z. Chen, P. Avouris","doi":"10.1109/DRC.2006.305182","DOIUrl":"https://doi.org/10.1109/DRC.2006.305182","url":null,"abstract":"Submitted for the MAR07 Meeting of The American Physical Society Characterization and Reduction of 1/f Noise in Carbon Nanotube Devices YU-MING LIN, PHAEDON AVOURIS, IBM T. J. Watson Research Center — 1/f noise is a ubiquitous fluctuation in semiconductors and metals. Unlike other types of fluctuations such as the thermal noise and the shot noise, 1/f noise increases with decreasing device dimension and is highly dependent on the material quality and interface properties. Therefore, the noise characteristics in nanoscaled devices are usually dominated by the 1/f-type fluctuations. Here we perform a systematic study on the 1/f noise of carbon nanotube devices consisting of individual single-wall carbon nanotubes. We have examined the impact of the contact and the substrate to the 1/f noise in carbon nanotube devices in order to reduce the 1/f noise level. By eliminating the charge traps associated with oxide substrates, we found that the 1/f noise in carbon nanotube devices can be lowered by up to two orders of magnitude. These results reveal important factors contributing to the 1/f noise source in carbon nanotube devices, and are of great importance for applications based on carbon nanotubes. Yu-Ming Lin IBM T. J. Watson Research Center Date submitted: 20 Nov 2006 Electronic form version 1.4","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129100899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Numerical Simulation of Field-Induced Inter-Band Tunneling Effect Transistor Using TCAD-Based Device Simulator 基于tcad的器件模拟器对场致带间隧道效应晶体管的数值模拟

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305147

K. Kim, Byung-Gook Park, R. Dutton

{"title":"Numerical Simulation of Field-Induced Inter-Band Tunneling Effect Transistor Using TCAD-Based Device Simulator","authors":"K. Kim, Byung-Gook Park, R. Dutton","doi":"10.1109/DRC.2006.305147","DOIUrl":"https://doi.org/10.1109/DRC.2006.305147","url":null,"abstract":"The field-induced inter-band tunneling effect transistor FITET is a practical quantum-tunneling device based on an SOI CMOS structure having both negative-differential transconductace (NDT) and negative-differential conductance (NDC) characteristics [1-3]. For the efficient simulation of these devices, exploiting band-to-band tunneling (BTBT) effects, we have previously developed numerical forward BTBT model and obtained NDC simulation results in 2-terminal silicon tunnel diodes [4]. In this paper, we performed the numerical simulation and device engineering for 3-terminal FITET structure by exploiting calibrated parameters from the forward BTBT model [4] in the commercial device simulator DESSIS [5]. Fig. 1 shows the numerical simulation results of transfer IV characteristics for the SOI CMOS structure with LG= 130 nm, tox= 3 nm, and tsoi= 40 nm. We designed long channel device to get rid of secondary parasitic effects such as short channel effects and gate tunneling. In the new local BTBT model for a body doping concentration of 1x1020/cm3, NDT characteristics are successfully simulated as in the previous experimental data [1,2], while the conventional BTBT model [6] cannot describe the observed NDT characteristics. In Fig. 2(a), we confirm the maximum band alignment between source and body in n-FITET case when VGS is 2.8 V, which is the peak voltage in the NDT curve of Fig. 1. Then, the forward BTBT in the source-to-body junction is suppressed as the body potential increases (band and quasi-fermi energy decreases) due to the injection of the excess hole carriers into the p+-doped floating body through reverse BTBT in the drain-to-body tunnel junction (Fig. 2 (b)). In the simulation of output I-V characteristics for the n-FITET (Fig. 3(a)), the NDC curve at VGS= 2.8 V also has been obtained and two output curves at VGS= 2.8 V and VGS= 3.2 V cross as in the experimental results ofp-FITET of Fig. 3(b) [3]. As shown in Fig. 4(a), BTBT current can be generated between the forward tunnel junction on the source side to the reverse tunnel junction of the drain side through the energy band alignment since the body potential decreases when VGS is 2.8 V where maximum depletion occurred in the body region. For a higher gate voltage of 3.4 V, the body potential increases due to the injection of the excess hole carriers in the floating body due to the increased reverse field between drain and gate, and then the BTBT current is suppressed at the same drain bias VDS= 0.1 V (Fig. 4(b)). The gate field effect on the tunnel junction plays a key role in the NDT/NDC characteristics of FITET. Figure 5, which shows a 2-dimensional contour plot of the electric field at VGS= 2.8 V, indicates that a strong electric field has been generated by the gate field, especially at the region between the junction and gate oxide interface where lateral (x-direction) junction and perpendicular gate field (y-direction) are superposed. We observed the BTBT rate with a maximum value ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125433768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

GaAs MOS Capacitors and Self-Aligned MOSFETs with HfO2 Gate Dielectrics 具有HfO2栅极介质的GaAs MOS电容器和自对准mosfet

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305111

S. Koester, E. Kiewra, Yanning Sun, D. Neumayer, J. Ott, D. Sadana, D. Webb, J. Fompeyrine, J. Locquet, M. Sousa, R. Germann

{"title":"GaAs MOS Capacitors and Self-Aligned MOSFETs with HfO2 Gate Dielectrics","authors":"S. Koester, E. Kiewra, Yanning Sun, D. Neumayer, J. Ott, D. Sadana, D. Webb, J. Fompeyrine, J. Locquet, M. Sousa, R. Germann","doi":"10.1109/DRC.2006.305111","DOIUrl":"https://doi.org/10.1109/DRC.2006.305111","url":null,"abstract":"Introduction: The difficulty of increasing performance by scaling in sub-100 nm Si CMOS technology has renewed interest in the use of Ill-V channel materials for advanced VLSI CMOS [1]. GaAs is an attractive choice for this application, due to its relative maturity compared to other III-Vs, its high electron mobility (6x compared to Si), and its lattice matching with Ge. The main barrier towards implementing GaAs for VLSI applications is the difficulty of forming a high-quality gate insulator [2]-[6]. However, other problems also need to be overcome, including poor thermal stability, low implant activation, and the lack of a self-aligned contacting scheme. In this work, we seek to address the integration and gate dielectric issues. We have developed a self-aligned process for GaAs MOSFETs with HfO2 gate dielectrics, and demonstrate functional enhancementand depletion-mode devices. We have also characterized MOS capacitors with GaAs/u-Si/SiO2/HfO2 gate stacks, and found that these structures have much lower DA and improved thermal stability compared to HfO2 films directly on GaAs.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115997596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0