2006 64th Device Research Conference最新文献

{"title":"Spintronics - from materials through devices to circuits -","authors":"H. Ohno","doi":"10.1109/DRC.2006.305094","DOIUrl":"https://doi.org/10.1109/DRC.2006.305094","url":null,"abstract":"Spintronics is the field in which both charge and spin degrees of freedom are used to realize functions otherwise not accessible. A wide variety of research is being carried out from those that are more exploratory in nature to close to the real world applications, from novel spin based semiconductor device structures to magnetic material-semiconductor hybrid structures not only for magnetic random access memories but for nonvolatile logic applications. Here, the author gives a personal overview of recent developments and perspective; first focusing on metal-based spintronics and then on semiconductor spintronics.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129274742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparing High Mobility InGaAs FETs with Si and GOI Devices","authors":"C. Liao, H. Kao, A. Chin, D. Yu, M. Li, C. Zhu, S. Mcalister","doi":"10.1109/DRC.2006.305130","DOIUrl":"https://doi.org/10.1109/DRC.2006.305130","url":null,"abstract":"We demonstrate a dislocation-free InAlAs/InGaAs/InAlAs-on-Insulator (IIIVOI) HEMT on a Si substrate, which has a high drain current and 8,100 cm2/Vs mobility. To reduce the Schottky gate leakage current in the device, a high-¿ Al2O3/InGaAs gate stack was used. By using this structure the gate leakage current was lower than that for a SiO2/Si MOSFET at the same equivalent-oxide-thickness (EOT), and the measured 451 cm2/Vs effective mobility was 2.5X higher.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130791556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"50 nm AlGaN/GaN HEMT Technology for mm-wave Applications","authors":"T. Palacios, N. Fichtenbaum, S. Keller, S. Denbaars, U. Mishra","doi":"10.1109/DRC.2006.305137","DOIUrl":"https://doi.org/10.1109/DRC.2006.305137","url":null,"abstract":"AlGaN/GaN high electron mobility transistors (HEMTs) have shown in the last few years an important increase in their high frequency performance, both at small and large signal levels. In 2005, Higashiwaki et al. and then Palacios et al. demonstrated a maximum current gain cut-off frequency of 163 GHz in unpassivated devices with a gate length of 60 and 90 nm respectively. Shortly after, Palacios et al. used a sacrificial Ge layer to reduce the parasitic capacitances and demonstrate a maximum fT of 153 GHz and an fmax of 185 GHz in passivated devices with Lg 90 nm. Recent output power measurements in excess of 10 W/mm at 40 GHz have demonstrated the tremendous potential of this material system for power amplification at mm-wave frequencies. All these results have motivated a high interest to expand the operating frequency of GaN-based transistors above 94 GHz. To get these very high operating frequencies, devices with extremely short gate lengths are necessary. This paper demonstrates a new deep submicron AlGaN/GaN technology based on the use of dielectric sidewalls to reduce the gate length of these devices down to 50 nm. All the samples used in this work were grown by metalorganic chemical vapor deposition (MOCVD) on SiC substrates. The sample structure consisted on a GaN buffer layer, followed by a 1 nm InO 1Ga0o9N backbarrier, 5 nm GaN channel, 0.6 nm AlN interlayer and 25 nm AlO 32Ga0 68N cap layer. During the processing of the devices, a metal stack of Ti/Al/Ni/Au was used for the ohmic contacts and annealed at 870°C for 30 s. Then, mesa isolation was performed with a C12-based reactive ion etching. The sample was passivated with a PECVD SiN layer. To reduce the parasitic gate capacitances in the deep submicron gates, a Ge sacrificial layer was deposited on top of the SiN passivation. After the Ge evaporation, the sample is coated with a ZEON ZEP-520 e-beam resist layer and the ebeam lithography of the foot of the gate is performed. During this lithography, gate structures with lengths in the 100-150 nm range were defined. A two-step dry etch process based on CHF3/CF4/02 plasmas was used to transfer the gate foot to the Ge and SiN layers. To shrink the gate lengths of these devices even further, a SiN layer was deposited conformably by PECVD. The SiN sidewalls deposited in this way reduced the gate length down to 50 nm. A CF4/02 plasma was used to remove the SiN from the top of the Ge sacrificial layer and from the bottom of the gate foot. This etch step is critical to assure a good gate morphology. Early attempts to develop a deep submicron sidewall technology had the problem of how to fill up the foot of the gate with the metal. In our novel approach, we use the higher etch rate of SiN against Ge to reduce the height of the SiN sidewall with respect to the top of the Ge sacrificial layer. As shown in Figure 1, this difference in height will allow the successful metallization of the gate. The top of the gate is defined by a second e-beam li","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123728272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A field-programmable antifuse memory for RFID on plastic","authors":"B. Mattis, V. Subramanian","doi":"10.1109/DRC.2006.305063","DOIUrl":"https://doi.org/10.1109/DRC.2006.305063","url":null,"abstract":"We demonstrate an integrated field-programmable nonvolatile memory technology on plastic, thus realizing a low-cost memory technology for systems on plastic such as RFID tags and sensors that require post-fabrication encoding with unique ID numbers. The crossbar memory array is integrated with steering diodes for every memory element, thus ensuring excellent addressability and scalability to large array sizes. Pentacene-aluminum schottky diodes were combined with a polyvinylphenol (PVP) dielectric to create field programmable nonvolatile memory crossbar arrays on a flexible PEN substrate. Our devices show high programmed/unprogrammed current margins (up to 10,000) at read voltages of 6V. Programming voltages are >20V, providing excellent read-write margin.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123113051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Gan-on-Silicon Based Technology for RF Cellular and Wimax Infrastructure Applications","authors":"K. Linthicum, A. Chaudhari, J. Cook, A. Edwards, A. Hanson, J. Johnson, I. Kizilyalli, T. Li, J. Marquart, W. Nagy, C. Park, E. Piner, P. Rajagopal, S. Singhal, R. Therrien, J. Willamson","doi":"10.1109/DRC.2006.305160","DOIUrl":"https://doi.org/10.1109/DRC.2006.305160","url":null,"abstract":"A GaN-on-silicon platform technology hasbeendeveloped toprovide theRF-device performance advantages ofgallium nitride combined withthemanufacturing advantages ofsilicon. A GaNFETprocess baseline hasbeenestablished tomeetthetransistor and amplifier performance demands ofUMTS andWiMaxapplications requiring higher CW powerandefficiency, higher operating voltage, broader bandwidth, higher frequency, and better linearity underW-CDMA andOFDM modulation neededbythewireless infrastructure markets. Nitronex hasusedacommonprocess baseline toscale gate peripheries, optimize internal matching networks andutilize various packaging solutions todevelop several products andinthis study wereport ontheNPT21120, NPT35010 and NPT35050whichspanperformance from2.1 - 3.5GHzandsaturated powerlevels from IOWto120W. AlGaN/GaN heterostructure field effect transistors havebeengrownandfabricated on float-zone 100mmsilicon (111) substrates bymetalorganic chemical vapor deposition [1]. Complete details ofthedevice processing havebeenpresented elsewhere [2].The baseline process includes useofsource field plates, 0.5-micron gatelengths andsource grounded backside vias.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116179436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reduction of 1/f Noise in Carbon Nanotube Devices","authors":"Y. Lin, J. Appenzeller, C. Tsuei, Z. Chen, P. Avouris","doi":"10.1109/DRC.2006.305182","DOIUrl":"https://doi.org/10.1109/DRC.2006.305182","url":null,"abstract":"Submitted for the MAR07 Meeting of The American Physical Society Characterization and Reduction of 1/f Noise in Carbon Nanotube Devices YU-MING LIN, PHAEDON AVOURIS, IBM T. J. Watson Research Center — 1/f noise is a ubiquitous fluctuation in semiconductors and metals. Unlike other types of fluctuations such as the thermal noise and the shot noise, 1/f noise increases with decreasing device dimension and is highly dependent on the material quality and interface properties. Therefore, the noise characteristics in nanoscaled devices are usually dominated by the 1/f-type fluctuations. Here we perform a systematic study on the 1/f noise of carbon nanotube devices consisting of individual single-wall carbon nanotubes. We have examined the impact of the contact and the substrate to the 1/f noise in carbon nanotube devices in order to reduce the 1/f noise level. By eliminating the charge traps associated with oxide substrates, we found that the 1/f noise in carbon nanotube devices can be lowered by up to two orders of magnitude. These results reveal important factors contributing to the 1/f noise source in carbon nanotube devices, and are of great importance for applications based on carbon nanotubes. Yu-Ming Lin IBM T. J. Watson Research Center Date submitted: 20 Nov 2006 Electronic form version 1.4","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129100899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Detecting high concentration hydrogen with nanoporous palladium supported by anodic aluminum oxides","authors":"D. Ding, Z. Chen","doi":"10.1109/DRC.2006.305151","DOIUrl":"https://doi.org/10.1109/DRC.2006.305151","url":null,"abstract":"Hydrogen-induced blistering of dense Pd films upon absorption of high concentration hydrogen is one of the big problems for hindering wide application of Pd-film hydrogen sensors fabricated on traditional wafers [1, 2]. Considerable stressing in the Pd film or stress mismatch at the interface between the Pd film and the supporting substrate is believed to cause such a failure in detecting high concentration hydrogen. In this work, we report hydrogen sensing properties of highly stable nanoporous Pd sensors fabricated on anodic aluminum oxides (AAOs). Aluminum film was deposited onto Ti-coated n-type Si wafers by e-beam evaporation. Through anodization of the Al film in 0.3 M oxalic acid, AAO substrate with pore diameters around 60 nm and pore lengths about 2.5 ,um was prepared. Nanoporous Pd films with a thickness of 45 nm or 5 nm were deposited, via r. f. sputtering, onto the AAO substrate by using Ni (2 nm in thickness) as a transition layer. The nanoporous Pd film sensors were put into a flask chamber. Resistive testing of the sensors under different concentrations of hydrogen gas was conducted with a Keithley 2000 multimeter. For comparison, dense Pd film sensors supported by silica wafers were also tested. Fig. 1 shows SEM morphologies of a dense Pd film and nanoporous Pd films. All of the sensors are sensitive to hydrogen gas at concentrations above 0.25% (Fig. 2). But the sensors made from the dense Pd films fail, by showing irreversible recovery (a sign of blistering) after switching off the hydrogen gas, at hydrogen concentrations above 1.5% for the 45 nm film and 3% for the 5 nm film. This once again proves that a blistering of dense Pd films will result in a failure to detect high concentration hydrogen. Whereas, the nanoporous Pd film sensors can detect much higher hydrogen concentrations up to 10%. At hydrogen concentrations above 1%, more than 20% of sensitivity (variation of film resistance upon absorption of H) can be obtained with the thicker nanoporous film (45 nm). At 12 concentrations above 2%, it only needs less than 30 seconds for the thicker nanoporous Pd film (45nm) to have a 10% variation of resistance (Fig. 3). With the film thickness being thinned down to 5 nm, the nanoporous film sensor has a much quicker response (Fig. 4). Typical response time of the thinner nanoporous Pd film (5nm) is less than 1 minute at 12 concentrations above 2%. And the response time decreases from 30 seconds at 4% 12 to 15 seconds at 10% 12. In comparison with dense Pd films deposited on traditional wafers, nanoporous Pd films shaped by the AAO nanotemplate can have a quick and reversible response to high concentration hydrogen without a blistering. Such a good mechanical stability indicates that the AAO substrate used here can help to stabilize the Pd films. Theoretically, a rough surface (including porous surface) can give an anchor effect to any deposited films and thus enhance the adhesion between deposited film and the substrate [3]. And ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121063028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Low-Cost Strained Silicon SRAM Technology with Reduced Contact Resistance","authors":"I. Polishchuk, S. Levy, R. Kapre, O. Pohland, K. Ramkumar, Nirav R. Shah, S. Thompson","doi":"10.1109/DRC.2006.305174","DOIUrl":"https://doi.org/10.1109/DRC.2006.305174","url":null,"abstract":"This paper presents a simple and cost-effective method to enhance 65nm SRAM technology performance using a single stress liner, resulting in 25% increase in cell read current. A novel slot contact process allows significant improvement of NMOS drive current without PMOS degradation, by relaxing the undesirable strain in the PMOS. This new slot process also results in significant reduction of the S/D contact resistance.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132066663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Progress in Silicon Carbide Power Devices","authors":"A. Agarwal, M. Das, B. Hull, S. Krishnaswami, J. Palmour, J. Richmond, S. Ryu, J. Zhang","doi":"10.1109/DRC.2006.305164","DOIUrl":"https://doi.org/10.1109/DRC.2006.305164","url":null,"abstract":"SiC materials and device technology has entered a new era with the commercialization and acceptance of 600 V/10 A and 1200 V/10 A Schottky Barrier Diodes (SBDs) in the marketplace. These diodes are finding applications in the Power Factor Correction (PFC) stage of Switch Mode Power Supplies (SMPS). SiC power MOSFETs with ratings of 800-1200 V up to 10 A will soon be commercially available. The next step is to integrate the SiC MOSFET and Schottky diodes in a power module for PFC and motor control applications. For high temperature applications, greater than 200°C, a bipolar switch such as a SiC BJT offers superior performance over the MOSFETs. The lack of gate oxide in the BJT offers better reliability at such extreme temperatures, in addition to the lowest combined switching and conduction losses.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114318386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Numerical Simulation of Field-Induced Inter-Band Tunneling Effect Transistor Using TCAD-Based Device Simulator","authors":"K. Kim, Byung-Gook Park, R. Dutton","doi":"10.1109/DRC.2006.305147","DOIUrl":"https://doi.org/10.1109/DRC.2006.305147","url":null,"abstract":"The field-induced inter-band tunneling effect transistor FITET is a practical quantum-tunneling device based on an SOI CMOS structure having both negative-differential transconductace (NDT) and negative-differential conductance (NDC) characteristics [1-3]. For the efficient simulation of these devices, exploiting band-to-band tunneling (BTBT) effects, we have previously developed numerical forward BTBT model and obtained NDC simulation results in 2-terminal silicon tunnel diodes [4]. In this paper, we performed the numerical simulation and device engineering for 3-terminal FITET structure by exploiting calibrated parameters from the forward BTBT model [4] in the commercial device simulator DESSIS [5]. Fig. 1 shows the numerical simulation results of transfer IV characteristics for the SOI CMOS structure with LG= 130 nm, tox= 3 nm, and tsoi= 40 nm. We designed long channel device to get rid of secondary parasitic effects such as short channel effects and gate tunneling. In the new local BTBT model for a body doping concentration of 1x1020/cm3, NDT characteristics are successfully simulated as in the previous experimental data [1,2], while the conventional BTBT model [6] cannot describe the observed NDT characteristics. In Fig. 2(a), we confirm the maximum band alignment between source and body in n-FITET case when VGS is 2.8 V, which is the peak voltage in the NDT curve of Fig. 1. Then, the forward BTBT in the source-to-body junction is suppressed as the body potential increases (band and quasi-fermi energy decreases) due to the injection of the excess hole carriers into the p+-doped floating body through reverse BTBT in the drain-to-body tunnel junction (Fig. 2 (b)). In the simulation of output I-V characteristics for the n-FITET (Fig. 3(a)), the NDC curve at VGS= 2.8 V also has been obtained and two output curves at VGS= 2.8 V and VGS= 3.2 V cross as in the experimental results ofp-FITET of Fig. 3(b) [3]. As shown in Fig. 4(a), BTBT current can be generated between the forward tunnel junction on the source side to the reverse tunnel junction of the drain side through the energy band alignment since the body potential decreases when VGS is 2.8 V where maximum depletion occurred in the body region. For a higher gate voltage of 3.4 V, the body potential increases due to the injection of the excess hole carriers in the floating body due to the increased reverse field between drain and gate, and then the BTBT current is suppressed at the same drain bias VDS= 0.1 V (Fig. 4(b)). The gate field effect on the tunnel junction plays a key role in the NDT/NDC characteristics of FITET. Figure 5, which shows a 2-dimensional contour plot of the electric field at VGS= 2.8 V, indicates that a strong electric field has been generated by the gate field, especially at the region between the junction and gate oxide interface where lateral (x-direction) junction and perpendicular gate field (y-direction) are superposed. We observed the BTBT rate with a maximum value ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125433768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}