2006 64th Device Research Conference最新文献

{"title":"Novel inorganic materials for solution-processed electronics","authors":"D. Talapin, D. Mitzi, E. Shevchenko, A. Alivisatos, Christopher Murray","doi":"10.1109/DRC.2006.305185","DOIUrl":"https://doi.org/10.1109/DRC.2006.305185","url":null,"abstract":"While conventional crystalline inorganic semiconductors offer superior charge carrier mobilities, they are generally difficult to form by low cost processes. Crystallization of inorganic semiconductors requires high-temperature treatments that force trade-offs between device performance, cost and compatibility with plastic substrates. The development of applications ranging from displays, photovoltaic cells and light-emitting devices to \"smart cards\", radio frequency tags and sensors could be accelerated by introducing lower cost alternatives to conventional silicon technology. Solution-based processes such as spin coating, dip coating or inkjet printing offer substantial cost reductions for fabrication of electronic and optoelectronic devices. We provide an overview of several new approaches to solution-processed inorganic semiconductors. Colloidal semiconductor nanocrystals enable room temperature solution-based fabrication of field-effect devices [1]. We fabricated thin-film transistor channels formed by self-assembly of 9 nm PbSe nanocrystals (Figure 1). Cross-linking of the nanocrystals with hydrazine increased exchange coupling, raising film conductance by about 10 orders of magnitude, yielding n-type device with charge-carrier mobility of 1 cm2/Vs. Reversible switching between nand p-type transport in nanocrystal arrays is possible upon adsorption of nor p-type doping molecules on nanocrystal surface (Figure 1d). Annealing of doped nanocrystal arrays at 200°C increased carrier mobility by about an order of magnitude. Electron mobility of 11 cm2/Vs was observed for arrays of 8 nm PbTe nanocrystals [2]. Self-assembly of multifunctional nanoparticle building blocks provides a powerful modular approach to the design of composite materials that combine properties of semiconducting, metallic and magnetic constituents (Figure 2) [3]. We demonstrate that these materials can be employed for solution-processed electronic and optoelectronic devices. Liquid-phase colloidal synthesis allows engineering size, shape and composition of nanomaterials. Various semiconductors can be prepared in form of nanoscale spheres, rods, discs, tetrapods, nanowires and nanorings. Some of these structures are interesting for ultra-small electronic devices. For example, Figure 3 shows a single electron transistor based on a CdTe tetrapod with arms 8 nm in diameter and 150 nm in length [5]. Another promising approach to solution-processed semiconductors is based on using molecular precursors that transform into crystalline inorganic semiconductors upon heating at elevated temperatures. A novel class of inexpensive soluble precursors for high-mobility inorganic chalcogenides has been developed [4]. For example, spin-coated films of In2Se3 exhibited electron mobilities as high as 16 cm2/Vs (Figure 4) [6]. Soluble hydrazine-based precursors can be synthesized for a range of materials with promising electronic, thermoelectric, and photovoltaic properties.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132853461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Spin-dependent Transport in Spin-photodiode Consisting of a p-n III-V Heterojunction","authors":"T. Kondo, J. Hayafuji, H. Munekata","doi":"10.1109/DRC.2006.305145","DOIUrl":"https://doi.org/10.1109/DRC.2006.305145","url":null,"abstract":"Understanding spin-dependent transport in semiconductor structures is very important to realize semiconductor spintronics devices. Early theoretical works have suggested unique spin-dependent transport phenomena in semiconductor structures having spatially inhomogeneous spin splitting in the conduction and/or valence bands [1,2]. Spin-voltaic effect (SVE), an electromotive force caused by the spin splitting, is one of such phenomena proposed for the homogeneous and graded p-n junctions [3,4]. SVE is useful for electrical detection of spin polarization. Utilizing this effect, we proposed and are working experimentally on \"spin-photodiode\" (spin-PD) which directly converts circular polarization of light into an electrical signal [5]. This device should be built by semiconductor layers with different g-factor and thus different band gap, we must understand spin transport across the heterointerface having finite band discontinuities. This paper describes theoretical treatments and experimental results of spin-dependent transport in a spin-PD consisting of a p-n, Ill-V heterojunction in which conduction band inp-region is spin-split (Fig. 1). Let us consider optical spin-injection into n-layer by right-circularly-polarized (es) light irradiation under the forward bias (Vf) condition. The optical spin-injection results in a spin polarization P11 of electrons in the n-layer. Applying the thermionic-diffusion theory [6,7] to this situation, a photocurrent due to SVE [3], AIsvE, can be expressed as follows;","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130332810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Hybrid silicon evanescent lasers","authors":"J. Bowers, A. Fang, Hyundai Park, O. Cohen, Richard Jones, M. Paniccia","doi":"10.1109/DRC.2006.305096","DOIUrl":"https://doi.org/10.1109/DRC.2006.305096","url":null,"abstract":"Silicon photonic platforms have been of great interest for the integration of photonic and electronic circuits on a silicon substrate. However, efficient light generation inside a silicon crystal has been the major obstacle due to the indirect bandgap characteristics of silicon. To overcome this problem, recently we demonstrated optically pumped hybrid silicon evanescent lasers, in which III-V based quantum wells are bonded to silicon rib waveguides. This approach enables to build active silicon photonic devices by combining high optical gain of Ill-V materials with well developed silicon processing technology. The work presented here is a first step of the future development of the electrically driven silicon active photonic devices as well as the photonic integration with electrical circuitry on silicon-on-insulator (SOI) wafers.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132404466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"50 nm AlGaN/GaN HEMT Technology for mm-wave Applications","authors":"T. Palacios, N. Fichtenbaum, S. Keller, S. Denbaars, U. Mishra","doi":"10.1109/DRC.2006.305137","DOIUrl":"https://doi.org/10.1109/DRC.2006.305137","url":null,"abstract":"AlGaN/GaN high electron mobility transistors (HEMTs) have shown in the last few years an important increase in their high frequency performance, both at small and large signal levels. In 2005, Higashiwaki et al. and then Palacios et al. demonstrated a maximum current gain cut-off frequency of 163 GHz in unpassivated devices with a gate length of 60 and 90 nm respectively. Shortly after, Palacios et al. used a sacrificial Ge layer to reduce the parasitic capacitances and demonstrate a maximum fT of 153 GHz and an fmax of 185 GHz in passivated devices with Lg 90 nm. Recent output power measurements in excess of 10 W/mm at 40 GHz have demonstrated the tremendous potential of this material system for power amplification at mm-wave frequencies. All these results have motivated a high interest to expand the operating frequency of GaN-based transistors above 94 GHz. To get these very high operating frequencies, devices with extremely short gate lengths are necessary. This paper demonstrates a new deep submicron AlGaN/GaN technology based on the use of dielectric sidewalls to reduce the gate length of these devices down to 50 nm. All the samples used in this work were grown by metalorganic chemical vapor deposition (MOCVD) on SiC substrates. The sample structure consisted on a GaN buffer layer, followed by a 1 nm InO 1Ga0o9N backbarrier, 5 nm GaN channel, 0.6 nm AlN interlayer and 25 nm AlO 32Ga0 68N cap layer. During the processing of the devices, a metal stack of Ti/Al/Ni/Au was used for the ohmic contacts and annealed at 870°C for 30 s. Then, mesa isolation was performed with a C12-based reactive ion etching. The sample was passivated with a PECVD SiN layer. To reduce the parasitic gate capacitances in the deep submicron gates, a Ge sacrificial layer was deposited on top of the SiN passivation. After the Ge evaporation, the sample is coated with a ZEON ZEP-520 e-beam resist layer and the ebeam lithography of the foot of the gate is performed. During this lithography, gate structures with lengths in the 100-150 nm range were defined. A two-step dry etch process based on CHF3/CF4/02 plasmas was used to transfer the gate foot to the Ge and SiN layers. To shrink the gate lengths of these devices even further, a SiN layer was deposited conformably by PECVD. The SiN sidewalls deposited in this way reduced the gate length down to 50 nm. A CF4/02 plasma was used to remove the SiN from the top of the Ge sacrificial layer and from the bottom of the gate foot. This etch step is critical to assure a good gate morphology. Early attempts to develop a deep submicron sidewall technology had the problem of how to fill up the foot of the gate with the metal. In our novel approach, we use the higher etch rate of SiN against Ge to reduce the height of the SiN sidewall with respect to the top of the Ge sacrificial layer. As shown in Figure 1, this difference in height will allow the successful metallization of the gate. The top of the gate is defined by a second e-beam li","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123728272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Detecting high concentration hydrogen with nanoporous palladium supported by anodic aluminum oxides","authors":"D. Ding, Z. Chen","doi":"10.1109/DRC.2006.305151","DOIUrl":"https://doi.org/10.1109/DRC.2006.305151","url":null,"abstract":"Hydrogen-induced blistering of dense Pd films upon absorption of high concentration hydrogen is one of the big problems for hindering wide application of Pd-film hydrogen sensors fabricated on traditional wafers [1, 2]. Considerable stressing in the Pd film or stress mismatch at the interface between the Pd film and the supporting substrate is believed to cause such a failure in detecting high concentration hydrogen. In this work, we report hydrogen sensing properties of highly stable nanoporous Pd sensors fabricated on anodic aluminum oxides (AAOs). Aluminum film was deposited onto Ti-coated n-type Si wafers by e-beam evaporation. Through anodization of the Al film in 0.3 M oxalic acid, AAO substrate with pore diameters around 60 nm and pore lengths about 2.5 ,um was prepared. Nanoporous Pd films with a thickness of 45 nm or 5 nm were deposited, via r. f. sputtering, onto the AAO substrate by using Ni (2 nm in thickness) as a transition layer. The nanoporous Pd film sensors were put into a flask chamber. Resistive testing of the sensors under different concentrations of hydrogen gas was conducted with a Keithley 2000 multimeter. For comparison, dense Pd film sensors supported by silica wafers were also tested. Fig. 1 shows SEM morphologies of a dense Pd film and nanoporous Pd films. All of the sensors are sensitive to hydrogen gas at concentrations above 0.25% (Fig. 2). But the sensors made from the dense Pd films fail, by showing irreversible recovery (a sign of blistering) after switching off the hydrogen gas, at hydrogen concentrations above 1.5% for the 45 nm film and 3% for the 5 nm film. This once again proves that a blistering of dense Pd films will result in a failure to detect high concentration hydrogen. Whereas, the nanoporous Pd film sensors can detect much higher hydrogen concentrations up to 10%. At hydrogen concentrations above 1%, more than 20% of sensitivity (variation of film resistance upon absorption of H) can be obtained with the thicker nanoporous film (45 nm). At 12 concentrations above 2%, it only needs less than 30 seconds for the thicker nanoporous Pd film (45nm) to have a 10% variation of resistance (Fig. 3). With the film thickness being thinned down to 5 nm, the nanoporous film sensor has a much quicker response (Fig. 4). Typical response time of the thinner nanoporous Pd film (5nm) is less than 1 minute at 12 concentrations above 2%. And the response time decreases from 30 seconds at 4% 12 to 15 seconds at 10% 12. In comparison with dense Pd films deposited on traditional wafers, nanoporous Pd films shaped by the AAO nanotemplate can have a quick and reversible response to high concentration hydrogen without a blistering. Such a good mechanical stability indicates that the AAO substrate used here can help to stabilize the Pd films. Theoretically, a rough surface (including porous surface) can give an anchor effect to any deposited films and thus enhance the adhesion between deposited film and the substrate [3]. And ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121063028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrical Performance of Ta-Based Ohmic Contacts on Undoped AlGaN/AlN/GaN Heterostructures","authors":"Yunju Sun, L. Eastman","doi":"10.1109/DRC.2006.305141","DOIUrl":"https://doi.org/10.1109/DRC.2006.305141","url":null,"abstract":"Undoped AlGaN/AIN/GaN Heterostructures Yunju Sun and L. F. Eastman 426 Phillips Hall, Cornell University, Ithaca NY 14853 E-mail: _ du Phone: 607-255-1431/607-342-0651 Fax: 607-255-4742 In order to improve the performance of the HFETs, the electrical characteristics of ohmic contacts formed on top of the heterostructures are extremely important in order to achieve a high transconductance and a high saturation current. Previously, thermally stable low resistance with SiCl4 plasma treatment was achieved using Ti/Al/Mo/Au multilayer ohmic contacts on n-GaN [1]. Its thickness and annealing condition were later optimized based on the electrical performance and edge acuity on Undoped AlGaN/GaN HEMTs structure without any plasma surface treatment [2]. The optimized thickness and annealing condition were Ti/Al/Mo/Au (15 nm/90 nm/40 nm/50 nm) and 800 for less than 30 sec respectively. In order to enhance the sheet charge confinement and improve electron mobility at heterojunction interface, a 10-15 A AlN interbarrier was inserted between AlGaN and GaN [3] HEMTs structure. From the experimental results, it was more difficult to get low contact resistance on Undoped AlGaN/GaN heterostructure with AlN interbarrier based on the same optimized Ti/Al/Mo/Au ohmic metal stack. In this report, in order to reduce the contact resistance, same material structure ( Undoped Al.27Ga.73N 230A/AlN 15A/GaN) was used, and Ta/Ti/Al/Mo/Au as a total of five metal layers with Ti/Al/Mo/Au fixed at 15 nm/90 nm/40 nm/50 nm and with Ta at a thickness of 30, 50, and 75 A respectively were evaporated on it. The electrical performance was also compared with the one using Ta/Ti/Al/Ti/Au metal layers on the same material structure. As shown in Fig. 1, with fixed Ti/Al/Mo/Au overlayers, a transfer resistance as low as 0.105 ohm-mm was obtained with Ta at a thickness of 75 A annealed at a cycle of 700 for 1 min followed by 800 for 20 sec. The transfer resistance increased as the Ta layer thickness decreased from 75 A to 30 A. Since comparing with the ohmic metal stack using Ti (4.33 eV) as a bottom layer, Ta has a lower work function (4.25 eV), it can be beneficial for the formation of low contact resistance. However, there could be a fluctuation of barrier height before the inner metal reaches a thickness that the metallic character of the film has been well established [4], which can be related to the dependence of contact resistance on the thickness of inner thin metal film. In Fig. 1, sheet resistance underneath the metal was also measured by \"end-resistance\" method, and the lowest value is 16.24 ohm/square for the one using 75 A Ta. Fig. 2 and Fig. 3 show the total resistance as a function ofTLM metal spacing with good linear fit (0.9997-0.9999) and I-V characteristics of ohmic contacts (9.5 ptm spacing) after annealing at 700 for 1 min followed by 800 for 20 sec respectively for Ti/Al/Mo/Au and Ti/Al/Ti/Au metal stack with an insertion of Ta as a bottom layer. As we can see, under ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126613286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Current Collapse-Free Vertical Submicron Channel GaN-based Transistors with InAlGaN Quaternary Alloy Contact Layers","authors":"T. Morita, S. Nakazawa, T. Ueda, Tsuyoshi Tanaka","doi":"10.1109/DRC.2006.305136","DOIUrl":"https://doi.org/10.1109/DRC.2006.305136","url":null,"abstract":"A GaN-based vertical transistor with good pinch-off characteristics at submicron channel is presented. An InAlGaN quaternary alloy contact layer on the top of the small post which serves non-alloy ohmic contact with WSi electrode, while virtually no current flows on a conventional n-GaN contact layer. A gate electrode is formed in a self-aligned manner using the overhang of the WSi contact as a mask. The fabricated vertical device does not exhibit current collapse which is commonly observed in planer AlGaN/GaN heterojunction transistors. Fig. 1 shows detailed schematic cross section of the fabricated vertical transistor. The epitaxial n-InAlGaN/ni-GaN/n+-GaN structure is grown on c-plane sapphire by metal organic chemical vapor deposition (MOCVD) technique. The Si doping concentration of the ni-GaN layer is in the order of 1017cm-3. The composition of the InAlGaN is chosen to be lattice matched to the underlying GaN. The InAlGaN alloy can serve non-alloy ohmic contacts due to its extremely low specific contact resistances originated from its large electron affinity [1]. After formation of the submicron epitaxial post by using the WSi electrode as a mask, PdSi gate electrode is formed in a self-aligned manner. The channel width is reduced down to 0.3ptm which can serve good pinch-off characteristics [2]. Bottom ohmic electrode is formed on the selectively exposed n+-GaN. The cross section and bird's view of the fabricated transistor observed by scanning electron microscope (SEM) are shown in Fig. 2, in which successful formation of the self-aligned gate is confirmed. Fig.3 shows typical drain current-voltage characteristics for 100ptm channel length device demonstrating working vertical transistor with good pinch-off characteristics. The obtained maximum lds at 1OV of Vd, is 240mA/mm corresponding to the high current density of 8OkA/cm2. The current density is almost one order of magnitude higher than that of conventional GaN-based planer device. The current-voltage characteristics between WSi ohmic and the gate exhibits good Schottky rectifying one with very low reverse leakage current as shown in Fig.4. The WSi contact exhibits good ohmic characteristics on the InAlGaN as shown in Fig.5, while no current flows on n-GaN. The obtained specific contact resistance of WSi on InAlGaN is 3.5x 10-5Qcm2. In addition to the high current density and small device size, vertical device configuration is also expected to be advantageous for suppressing the so-called current collapse because most of the channel region is not exposed on the surface and thus would not be affected by the surface traps. The current collapse is the phenomena in which drain current is collapsed after high drain bias is applied. In order to examine it, pulsed current-voltage characteristics are measured varying the maximum Vd, as shown in Fig.6 comparing the source-up and drain-up configurations. The used pulse width is 80isec. The applied maximum drain voltage is higher for the sourc","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126781901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrically-excited Infrared Emission from InN Nanowire Transistors","authors":"Jia Chen, G. Cheng, E. Stern, M. Reed, P. Avouris","doi":"10.1109/DRC.2006.305187","DOIUrl":"https://doi.org/10.1109/DRC.2006.305187","url":null,"abstract":"We report electrically excited infrared emission from a single InN nanowire transistor. We report on: (1) the generation of IR emission by impact excitation of carriers under a high electrical field, (2) the size of the fundamental band gap of InN NW by measuring its emission spectra, (3) the observation of interband and conduction-band to conduction-band hot-carrier emission, and the carrier relaxation rate, and finally, (4) we present evidence that suggests that the electron accumulation layer at the InN NW surface forms a surface plasmon that couples to and enhances radiative electron-hole pair recombination.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"489 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115300562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Gan-on-Silicon Based Technology for RF Cellular and Wimax Infrastructure Applications","authors":"K. Linthicum, A. Chaudhari, J. Cook, A. Edwards, A. Hanson, J. Johnson, I. Kizilyalli, T. Li, J. Marquart, W. Nagy, C. Park, E. Piner, P. Rajagopal, S. Singhal, R. Therrien, J. Willamson","doi":"10.1109/DRC.2006.305160","DOIUrl":"https://doi.org/10.1109/DRC.2006.305160","url":null,"abstract":"A GaN-on-silicon platform technology hasbeendeveloped toprovide theRF-device performance advantages ofgallium nitride combined withthemanufacturing advantages ofsilicon. A GaNFETprocess baseline hasbeenestablished tomeetthetransistor and amplifier performance demands ofUMTS andWiMaxapplications requiring higher CW powerandefficiency, higher operating voltage, broader bandwidth, higher frequency, and better linearity underW-CDMA andOFDM modulation neededbythewireless infrastructure markets. Nitronex hasusedacommonprocess baseline toscale gate peripheries, optimize internal matching networks andutilize various packaging solutions todevelop several products andinthis study wereport ontheNPT21120, NPT35010 and NPT35050whichspanperformance from2.1 - 3.5GHzandsaturated powerlevels from IOWto120W. AlGaN/GaN heterostructure field effect transistors havebeengrownandfabricated on float-zone 100mmsilicon (111) substrates bymetalorganic chemical vapor deposition [1]. Complete details ofthedevice processing havebeenpresented elsewhere [2].The baseline process includes useofsource field plates, 0.5-micron gatelengths andsource grounded backside vias.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116179436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Label-Free Amperometric Biosensors Based on Single-Walled Carbon Nanotube Modified Microelectrodes","authors":"K. Maehashi, J. Okuno, K. Matsumoto, K. Kerman, Y. Takamura, E. Tamiya","doi":"10.1109/DRC.2006.305047","DOIUrl":"https://doi.org/10.1109/DRC.2006.305047","url":null,"abstract":"Single-Walled Carbon Nanotube Modified Microelectrodes Kenzo Maehashil, Jun Okuno', Kazuhiko Matsumoto', Kagan Kerman2, Yuzuru Takamura2 and Eiichi Tamiya2 'The Institute ofScientific and Industrial Research, Osaka University, 8-1 Mihogaoka, Ibaraki, Osaka 567-0047, Japan 2School ofMaterials Science, Japan Advanced Institute ofScience and Technology, 1-1 Asahidai, Nomi, Ishikawa 923-1292, Japan E-mail: maehashigsanken.osaka-u.acjp/ Phone & Fax: +81-6-6879-8412","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116512044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}