2006 64th Device Research Conference最新文献_第9页

Novel inorganic materials for solution-processed electronics 溶液加工电子学用新型无机材料

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305185

D. Talapin, D. Mitzi, E. Shevchenko, A. Alivisatos, Christopher Murray

{"title":"Novel inorganic materials for solution-processed electronics","authors":"D. Talapin, D. Mitzi, E. Shevchenko, A. Alivisatos, Christopher Murray","doi":"10.1109/DRC.2006.305185","DOIUrl":"https://doi.org/10.1109/DRC.2006.305185","url":null,"abstract":"While conventional crystalline inorganic semiconductors offer superior charge carrier mobilities, they are generally difficult to form by low cost processes. Crystallization of inorganic semiconductors requires high-temperature treatments that force trade-offs between device performance, cost and compatibility with plastic substrates. The development of applications ranging from displays, photovoltaic cells and light-emitting devices to \"smart cards\", radio frequency tags and sensors could be accelerated by introducing lower cost alternatives to conventional silicon technology. Solution-based processes such as spin coating, dip coating or inkjet printing offer substantial cost reductions for fabrication of electronic and optoelectronic devices. We provide an overview of several new approaches to solution-processed inorganic semiconductors. Colloidal semiconductor nanocrystals enable room temperature solution-based fabrication of field-effect devices [1]. We fabricated thin-film transistor channels formed by self-assembly of 9 nm PbSe nanocrystals (Figure 1). Cross-linking of the nanocrystals with hydrazine increased exchange coupling, raising film conductance by about 10 orders of magnitude, yielding n-type device with charge-carrier mobility of 1 cm2/Vs. Reversible switching between nand p-type transport in nanocrystal arrays is possible upon adsorption of nor p-type doping molecules on nanocrystal surface (Figure 1d). Annealing of doped nanocrystal arrays at 200°C increased carrier mobility by about an order of magnitude. Electron mobility of 11 cm2/Vs was observed for arrays of 8 nm PbTe nanocrystals [2]. Self-assembly of multifunctional nanoparticle building blocks provides a powerful modular approach to the design of composite materials that combine properties of semiconducting, metallic and magnetic constituents (Figure 2) [3]. We demonstrate that these materials can be employed for solution-processed electronic and optoelectronic devices. Liquid-phase colloidal synthesis allows engineering size, shape and composition of nanomaterials. Various semiconductors can be prepared in form of nanoscale spheres, rods, discs, tetrapods, nanowires and nanorings. Some of these structures are interesting for ultra-small electronic devices. For example, Figure 3 shows a single electron transistor based on a CdTe tetrapod with arms 8 nm in diameter and 150 nm in length [5]. Another promising approach to solution-processed semiconductors is based on using molecular precursors that transform into crystalline inorganic semiconductors upon heating at elevated temperatures. A novel class of inexpensive soluble precursors for high-mobility inorganic chalcogenides has been developed [4]. For example, spin-coated films of In2Se3 exhibited electron mobilities as high as 16 cm2/Vs (Figure 4) [6]. Soluble hydrazine-based precursors can be synthesized for a range of materials with promising electronic, thermoelectric, and photovoltaic properties.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132853461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Spin-dependent Transport in Spin-photodiode Consisting of a p-n III-V Heterojunction 由p-n III-V异质结组成的自旋光电二极管中的自旋相关输运

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305145

T. Kondo, J. Hayafuji, H. Munekata

{"title":"Spin-dependent Transport in Spin-photodiode Consisting of a p-n III-V Heterojunction","authors":"T. Kondo, J. Hayafuji, H. Munekata","doi":"10.1109/DRC.2006.305145","DOIUrl":"https://doi.org/10.1109/DRC.2006.305145","url":null,"abstract":"Understanding spin-dependent transport in semiconductor structures is very important to realize semiconductor spintronics devices. Early theoretical works have suggested unique spin-dependent transport phenomena in semiconductor structures having spatially inhomogeneous spin splitting in the conduction and/or valence bands [1,2]. Spin-voltaic effect (SVE), an electromotive force caused by the spin splitting, is one of such phenomena proposed for the homogeneous and graded p-n junctions [3,4]. SVE is useful for electrical detection of spin polarization. Utilizing this effect, we proposed and are working experimentally on \"spin-photodiode\" (spin-PD) which directly converts circular polarization of light into an electrical signal [5]. This device should be built by semiconductor layers with different g-factor and thus different band gap, we must understand spin transport across the heterointerface having finite band discontinuities. This paper describes theoretical treatments and experimental results of spin-dependent transport in a spin-PD consisting of a p-n, Ill-V heterojunction in which conduction band inp-region is spin-split (Fig. 1). Let us consider optical spin-injection into n-layer by right-circularly-polarized (es) light irradiation under the forward bias (Vf) condition. The optical spin-injection results in a spin polarization P11 of electrons in the n-layer. Applying the thermionic-diffusion theory [6,7] to this situation, a photocurrent due to SVE [3], AIsvE, can be expressed as follows;","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130332810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hybrid silicon evanescent lasers 混合硅倏逝激光器

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305096

J. Bowers, A. Fang, Hyundai Park, O. Cohen, Richard Jones, M. Paniccia

引用次数: 3

Electrically-excited Infrared Emission from InN Nanowire Transistors InN纳米线晶体管的电激红外发射

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305187

Jia Chen, G. Cheng, E. Stern, M. Reed, P. Avouris

引用次数: 3

Label-Free Amperometric Biosensors Based on Single-Walled Carbon Nanotube Modified Microelectrodes 基于单壁碳纳米管修饰微电极的无标签安培生物传感器

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305047

K. Maehashi, J. Okuno, K. Matsumoto, K. Kerman, Y. Takamura, E. Tamiya

引用次数: 3

High-Speed Photodiodes and Related Devices 高速光电二极管及相关器件

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305051

T. Ishibashi, Hiroshi Ito

引用次数: 0

Current Collapse-Free Vertical Submicron Channel GaN-based Transistors with InAlGaN Quaternary Alloy Contact Layers 含InAlGaN四元合金接触层的无坍缩垂直亚微米gan基晶体管

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305136

T. Morita, S. Nakazawa, T. Ueda, Tsuyoshi Tanaka

{"title":"Current Collapse-Free Vertical Submicron Channel GaN-based Transistors with InAlGaN Quaternary Alloy Contact Layers","authors":"T. Morita, S. Nakazawa, T. Ueda, Tsuyoshi Tanaka","doi":"10.1109/DRC.2006.305136","DOIUrl":"https://doi.org/10.1109/DRC.2006.305136","url":null,"abstract":"A GaN-based vertical transistor with good pinch-off characteristics at submicron channel is presented. An InAlGaN quaternary alloy contact layer on the top of the small post which serves non-alloy ohmic contact with WSi electrode, while virtually no current flows on a conventional n-GaN contact layer. A gate electrode is formed in a self-aligned manner using the overhang of the WSi contact as a mask. The fabricated vertical device does not exhibit current collapse which is commonly observed in planer AlGaN/GaN heterojunction transistors. Fig. 1 shows detailed schematic cross section of the fabricated vertical transistor. The epitaxial n-InAlGaN/ni-GaN/n+-GaN structure is grown on c-plane sapphire by metal organic chemical vapor deposition (MOCVD) technique. The Si doping concentration of the ni-GaN layer is in the order of 1017cm-3. The composition of the InAlGaN is chosen to be lattice matched to the underlying GaN. The InAlGaN alloy can serve non-alloy ohmic contacts due to its extremely low specific contact resistances originated from its large electron affinity [1]. After formation of the submicron epitaxial post by using the WSi electrode as a mask, PdSi gate electrode is formed in a self-aligned manner. The channel width is reduced down to 0.3ptm which can serve good pinch-off characteristics [2]. Bottom ohmic electrode is formed on the selectively exposed n+-GaN. The cross section and bird's view of the fabricated transistor observed by scanning electron microscope (SEM) are shown in Fig. 2, in which successful formation of the self-aligned gate is confirmed. Fig.3 shows typical drain current-voltage characteristics for 100ptm channel length device demonstrating working vertical transistor with good pinch-off characteristics. The obtained maximum lds at 1OV of Vd, is 240mA/mm corresponding to the high current density of 8OkA/cm2. The current density is almost one order of magnitude higher than that of conventional GaN-based planer device. The current-voltage characteristics between WSi ohmic and the gate exhibits good Schottky rectifying one with very low reverse leakage current as shown in Fig.4. The WSi contact exhibits good ohmic characteristics on the InAlGaN as shown in Fig.5, while no current flows on n-GaN. The obtained specific contact resistance of WSi on InAlGaN is 3.5x 10-5Qcm2. In addition to the high current density and small device size, vertical device configuration is also expected to be advantageous for suppressing the so-called current collapse because most of the channel region is not exposed on the surface and thus would not be affected by the surface traps. The current collapse is the phenomena in which drain current is collapsed after high drain bias is applied. In order to examine it, pulsed current-voltage characteristics are measured varying the maximum Vd, as shown in Fig.6 comparing the source-up and drain-up configurations. The used pulse width is 80isec. The applied maximum drain voltage is higher for the sourc","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126781901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical Performance of Ta-Based Ohmic Contacts on Undoped AlGaN/AlN/GaN Heterostructures 未掺杂AlGaN/AlN/GaN异质结构上ta基欧姆触点的电学性能

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305141

Yunju Sun, L. Eastman

{"title":"Electrical Performance of Ta-Based Ohmic Contacts on Undoped AlGaN/AlN/GaN Heterostructures","authors":"Yunju Sun, L. Eastman","doi":"10.1109/DRC.2006.305141","DOIUrl":"https://doi.org/10.1109/DRC.2006.305141","url":null,"abstract":"Undoped AlGaN/AIN/GaN Heterostructures Yunju Sun and L. F. Eastman 426 Phillips Hall, Cornell University, Ithaca NY 14853 E-mail: _ du Phone: 607-255-1431/607-342-0651 Fax: 607-255-4742 In order to improve the performance of the HFETs, the electrical characteristics of ohmic contacts formed on top of the heterostructures are extremely important in order to achieve a high transconductance and a high saturation current. Previously, thermally stable low resistance with SiCl4 plasma treatment was achieved using Ti/Al/Mo/Au multilayer ohmic contacts on n-GaN [1]. Its thickness and annealing condition were later optimized based on the electrical performance and edge acuity on Undoped AlGaN/GaN HEMTs structure without any plasma surface treatment [2]. The optimized thickness and annealing condition were Ti/Al/Mo/Au (15 nm/90 nm/40 nm/50 nm) and 800 for less than 30 sec respectively. In order to enhance the sheet charge confinement and improve electron mobility at heterojunction interface, a 10-15 A AlN interbarrier was inserted between AlGaN and GaN [3] HEMTs structure. From the experimental results, it was more difficult to get low contact resistance on Undoped AlGaN/GaN heterostructure with AlN interbarrier based on the same optimized Ti/Al/Mo/Au ohmic metal stack. In this report, in order to reduce the contact resistance, same material structure ( Undoped Al.27Ga.73N 230A/AlN 15A/GaN) was used, and Ta/Ti/Al/Mo/Au as a total of five metal layers with Ti/Al/Mo/Au fixed at 15 nm/90 nm/40 nm/50 nm and with Ta at a thickness of 30, 50, and 75 A respectively were evaporated on it. The electrical performance was also compared with the one using Ta/Ti/Al/Ti/Au metal layers on the same material structure. As shown in Fig. 1, with fixed Ti/Al/Mo/Au overlayers, a transfer resistance as low as 0.105 ohm-mm was obtained with Ta at a thickness of 75 A annealed at a cycle of 700 for 1 min followed by 800 for 20 sec. The transfer resistance increased as the Ta layer thickness decreased from 75 A to 30 A. Since comparing with the ohmic metal stack using Ti (4.33 eV) as a bottom layer, Ta has a lower work function (4.25 eV), it can be beneficial for the formation of low contact resistance. However, there could be a fluctuation of barrier height before the inner metal reaches a thickness that the metallic character of the film has been well established [4], which can be related to the dependence of contact resistance on the thickness of inner thin metal film. In Fig. 1, sheet resistance underneath the metal was also measured by \"end-resistance\" method, and the lowest value is 16.24 ohm/square for the one using 75 A Ta. Fig. 2 and Fig. 3 show the total resistance as a function ofTLM metal spacing with good linear fit (0.9997-0.9999) and I-V characteristics of ohmic contacts (9.5 ptm spacing) after annealing at 700 for 1 min followed by 800 for 20 sec respectively for Ti/Al/Mo/Au and Ti/Al/Ti/Au metal stack with an insertion of Ta as a bottom layer. As we can see, under ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126613286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Accumulated Body MOSFET 累积体MOSFET

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305126

A. Gokirmak

{"title":"Accumulated Body MOSFET","authors":"A. Gokirmak","doi":"10.1109/DRC.2006.305126","DOIUrl":"https://doi.org/10.1109/DRC.2006.305126","url":null,"abstract":"Multi-gate MOSFET structures have been investigated in recent years for increased electrostatic control of the channel potential and electrostatic threshold voltage tunability. Multi-gate transistors typically have two parallel gates straddling the device body [1]. We have integrated additional side-gates to planar nMOSFETs fabricated on bulk Si platform using Si3N4 shallow trench isolation (STI) with 19 nm Si3N4 side-gate insulator, and 4 nm thermally grown SiO2 top-gate insulator (Fig. 1). The side-gate surrounds the active area such as a guard ring, and the top-gate is independently controlled [2]. The side-gates of the device are used to accumulate the side-interfaces with application of a negative bias, while the top-gate is used for transistor operation as in a conventional FET. Accumulation of the holes at the periphery results in significant reduction in defect assisted recombination current from drain to substrate at the side interfaces (Fig.2), thus increased defect tolerance and reliability for strained Si technologies [3]. As the device width is reduced, the side interfaces draw near, countering the depletion effects. This results in accumulation of the device body for narrow channel devices (Fig. Id). The narrow channel devices exhibit distinctly different characteristics depending on the channel width and the amount the side-gates are recessed below the level of active area (Fig. ib), resembling tri-gate FET [3], as opposed to being at the same level (Fig.Ic). The accumulation of the side-interfaces suppresses the peripheral Ids leakage along the Si-STI interfaces and eliminate the need for edge implants [5] while resulting in excellent characteristics, such as an lo,/Ioff > 6 x 1010 for aW x L = 0.6 pim x 0.3 pim device (Fig. 3,4). As the width of the device is reduced close to the depletion depth (Wd) in the channel region, the source, drain junction depletion are reduced, as well as depletion region under the gate. This results in suppression of leakage currents due to punch through and drain induced barrier lowering (DIBL) for short channel devices as a function Of VSid, (Fig. 5-8). The physical gate length of this device is estimated to be 69 nm from SEM and effective width (Weff) is estimated to be 150 nm from its C-V characteristics, indicating significant side-gate recess given that W,= 79 nm. Maximum drive current of this device exceeds 1.6 mA/ Im Weff. The effective mobility (4etff) calculated for a Weff= 23 nm, Leff 140 nm device is below 100 cm2 V-s (Fig. 9), however, the maximum saturation transconductance, gm = 0.74 mANV.im, result in an estimated electron saturation velocity of 8.6 x 106 cm/s [6]. At these device dimensions DIBL is suppressed below 10 mVNV. Planar accumulated body FETs with Weff < 10 nm exhibit extreme Vt response to VSid, (Fig. 10). Vt can be tuned from 1 V to 4 V within the -0.5 V < VSid, < -2 V range with sensitivity, Y = V/6Vside > -2.1 V/V in the -0.5 > Vside > -1 V regime. The threshold voltage ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114463721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Device, Circuit and System Dimensions of 3-D Integration 3-D集成的设备、电路和系统尺寸

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305106

S. Tiwari, Christianto C. Liu, S. Kim

引用次数: 0