2006 64th Device Research Conference最新文献

{"title":"Realization of a Ge nanowire p-n junction","authors":"Emanuel Tutuc, Joerg Appenzeller, Mark C. Reuter, Supratik Guha","doi":"10.1109/DRC.2006.305078","DOIUrl":"https://doi.org/10.1109/DRC.2006.305078","url":null,"abstract":"","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116246855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process development for the realization of thermally-reliable enhancement-mode InAlAs/InGaAs/InP HEMTs with excellent DC and RF performance","authors":"Weifeng Zhao, Niu Jin, Guang Chen, Vipan Kumar, I. Adesida","doi":"10.1109/DRC.2006.305133","DOIUrl":"https://doi.org/10.1109/DRC.2006.305133","url":null,"abstract":"Ohmic contact degradation and gate sinking (especially when Pt is used as the gate contact for E-HEMTs) are two of the major reliability concerns for the InAlAs/InGaAs/InP HEMTs [1, 2]. Thermally-stable Ohmic contacts based on Ge/Ag/Ni metallizations have recently been developed [3]. They are annealed at temperatures higher than those used for conventionally annealed-AuGe/Ni/Au ohmic contacts. Schottky contacts based on Iridium have been shown to have barrier heights as high as Platinum-based Schottky contacts [4]. E-HEMTs fabricated utilizing Ir-gate have demonstrated better thermal stability than Pt-gate E-HEMTs [4]. Using FATFETs and C-V measurements, it was demonstrated that no gate diffusion occurred in thermally-treated Ir-gate E-HEMTs whereas there was gate diffusion in Pt-gate devices [4]. In this work, we have combined the Ir-gate contact and Ge/Ag/Ni-ohmic contact technologies to fabricate high performance E-HEMTs with high thermal stability potential. The heterostructure used for this study was grown by molecular beam epitaxy on (100) semi-insulating InP substrate. The schematic is shown in Fig. 1. The sheet resistance, sheet carrier concentration, and electron mobility, as determined by Hall measurements, were 253 Q/z, 2.97 x 1012 cm-2 and 8295 cm2/V-S, respectively. Ohmic contact optimization process based on transmission line method (TLM) with metallization of Ge/Ag/Ni was first performed to determine the optimum annealing conditions for ohmic formation. Also, Schottky diodes using Ir/Ti/Pt/Au contact metallization were fabricated to study Schottky barrier height enhancement as a function of annealing temperature. Both the TLM samples and Schottky diodes were passivated using a 60-nm-thick SiNX layer prior to annealing in a rapid thermal annealing (RTA) system for 30 seconds. Device fabrication starts with mesa and sidewall isolations using a mixture of citric acid and hydrogen peroxide. The metallization of Ge/Ag/Ni was then deposited using electron beam evaporation and lift-off techniques for ohmic contact. T-shaped gate was defined by e-beam lithography system. The following recess procedure was performed after the gate definition: the 8-nm-thick Ino.53Ga047As contact layer and 6-nm-thick undoped In0o52A10o48As layer was first selectively removed using a citric acid/hydrogen peroxide solution. Then the first AlAs etch stop layer was removed by a solution of HCl and DI water in the ratio of 1: 2. Using the same solution of citric acid, the 3.5-nm-thick undoped Ino52A1048As D-HEMT barrier layer was subsequently removed followed by the removal of the second layer of AlAs etch stop by the same HCl solution that was used for the first AlAs layer. After the gate recess, Ir/Ti/Pt/Au were evaporated by e-beam evaporator. Before the ohmic and gate contacts were annealed simultaneously, a SiNX layer was deposited by PECVD. This SiNx layer also acted as the passivation layer for the final device. The sample was annealed at 425 °C for 30 sec","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115949996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Assessment of Carbon Nanotube FETs for High-Frequency Performance","authors":"D. Pulfrey","doi":"10.1109/DRC.2006.305169","DOIUrl":"https://doi.org/10.1109/DRC.2006.305169","url":null,"abstract":"The small size, unusual topography, and technological immaturity of carbon nanotube field-effect transistors (CNFETs) have contributed, no doubt, to the fact that the present record for their measured \"frequencyindependent performance\" is a modest 23 GHz [1]. For the moment, then, we need to rely on simulations to get a better idea of the high-frequency capability of CNFETs. Any field-effect transistor exhibiting good high-frequency performance is likely to have a high, intrinsic, short-circuit, unity-current-gain, frequency","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115982774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrating Spintronics with Conventional Semiconductor Devices through Exchange Interaction","authors":"S. Salahuddin, P. Srivastava, S. Datta","doi":"10.1109/DRC.2006.305071","DOIUrl":"https://doi.org/10.1109/DRC.2006.305071","url":null,"abstract":"The field of spintronics often requires one to be able to read and write spin information in an efficient way. Conventionally, writing is performed by putting strong magnetic fields whereas spin detection relies on various resonance techniques. Both these methods suffer from spatial resolution, technological incompatibility and lack of integrability. Here, we show that by utilizing the exchange interaction between the conduction electrons and a spin array, it is possible to devise an all-electrical scheme such that one can both read and write information from and to a spin array. This method could enable one to merge semiconductor based electronics with metal based magneto-electronics leading to a whole new class of devices.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134434352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Voltage 4H-SiC Epitaxial Emitter BJTs using a Self-aligned Selectively Re-grown Base Contact","authors":"S. Balachandran, C. Li, P. Losee, T. Chow, I. Bhat, A. Agarwal","doi":"10.1109/DRC.2006.305191","DOIUrl":"https://doi.org/10.1109/DRC.2006.305191","url":null,"abstract":"We demonstrate a novel self aligned selective re-growth based epitaxial emitter BJT and, for the first time, give evidence for the presence of conductivity modulation in SiC BJTs. The p+ contact region is selectively re-grown with Tantalum metal as the mask for the emitter mesa isolation etch after which it is carburized and used as a mask for the selective growth of p+ regions in the trenches. This makes the process self aligned. An isolation etch is then carried out to disconnect any sidewall contact between the p+ and the n+ regions. The devices were fabricated on two sets of drift layers: 1) 45μm, 1.1 x 1015 cm-3, and 2) 12μm, 4 x 1015 cm-3.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131652707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Random Telegraph Noise in 130 nm n-MOS and p-MOS Transistors","authors":"Youngchang Yoon, Hochul Lee, I. Kang, Byung-Gook Park, J. Lee, Hyungcheol Shin","doi":"10.1109/DRC.2006.305184","DOIUrl":"https://doi.org/10.1109/DRC.2006.305184","url":null,"abstract":"Introduction The low-frequency noise performance of MOSFETs is dominated by the effects of carrier trapping and de-trapping into oxide defects [1]. Capture and emission of a carrier by the single trap result in discrete modulation of the channel current which resembles a random telegraph signal. As the gate area of devices decreases, AId/ld fluctuations give a significant issue for advanced low power analog and mixedmode circuitry [2]. So it is very important to examine RTS noise characteristic of the small devices. It has been accepted that low frequency noise comes from both number and mobility fluctuations. In this paper, scattering coefficient (a) has been extracted through the analysis of the amplitude of the drain current fluctuations for 130 nm n-MOSFETs and pMOSFETs. The relative contribution of number and mobility fluctuations is examined and the effect of trap's depth on noise amplitude is also considered.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131620978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The new Shielded Bitline Sensing Method for FC-SGT Flash memory","authors":"Y. Yamakawa, H. Nakamura, F. Masuoka","doi":"10.1109/DRC.2006.305116","DOIUrl":"https://doi.org/10.1109/DRC.2006.305116","url":null,"abstract":"In this paper, we propose a new Shielded Bitline Sensing Method for Floating Channel Surrounding Gate Transistor (FC-SGT) Flash memory [1], which enable to suppress a bitline capacitance coupling noise without reducing its read throughput. The new shielding method is accomplished by the 3-D structure ofthe FC-SGT Flash memory and its high flexibility ofwiring. We illustrate a structure of the FC-SGT Flash memory cell in Fig.1 [1]. A channel region, whose shape is a pillar, is surrounded by a tunnel oxide, floating gate, inter-poly insulator, and control gate. A drain and source electrode are located at the end ofthe silicon pillar. All bitlines run parallel to sourcelines. The writing and erasing operation work with FN tunneling. Due to these own features, the FC-SGT Flash memory is suitable for the low-power operation and high density storage To operate a read sequence with the open bitline architecture, the bitline coupling capacitance generates a large bitline capacitance coupling noise. As shown in Fig.2, when nearest bitlines from a bitline are discharged, the bitline capacitance coupling noise A VNlbecomes the worst value, which is expressed by the Eql. Reading the FCSGT Flash memory cell with conventional open bitline architecture, we now calculate the bitline capacitance coupling noise. According to ITRS 2005's parameters [2] and plate capacitance assumption (see Fig.3), we can calculate that the bitline coupling noises becomes Eq2. IfVpc equal 1.8V, the charged bittlines are discharged from 1.8V to 0.83V. So, it is difficult to read the content ofthe operated cell. And the more dense memory cells become, the larger bitline capacitance coupling noise become. In order to solve this problem, the Shielded Bitline Sensing Method has been proposed [3]. Fig.4 shows the equivalent circuitry of the Shielded Bitline Sensing Method. It is that the pre-charge voltage Vpc is applied to every second bitlines, while left of bitlines are connected to the GND. Then we obtain the suppressed noise value A VN3X which is given by Eq3. The Cbitl is very smaller than the Cbit2, so we can almost neglect the bitline capacitance coupling noise. In case ofthe conventional shielded bitline sensing method, we can not operate all bitlines simultaneously. So as to read all bitlines at the same time, we propose novel Shielded Bitline Sensing Method for FC-SGT Flash memory. We describe the memory cell array ofthe FC-SGT Flash memory in Fig.5. The new shielding scheme is realized by its 3-D structure and unique memory cell array. The equivalent circuit and bird's eye view of the memory cell, which use new Shielded Bitline Sensing Method for FC-SGT Flash memory, are illustrated as Fig.6 (a) and (b) respectably. Fig.6 (a) and (b) show the same condition. The bitline and sourceline is located by tumns. It is that the pre-charge voltage Vpc is applied to bitlines. In the other hands, sourcelines are connected to the GND. Hence the voltage difference between a bitline and its","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129293630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Sub-6F2 Charge Trap Dynamic Random Access Memory Using a Novel Operation Scheme","authors":"Z. Huo, Seungjae Baik, S. Kim, I. Yeo, U. Chung, J. Moon","doi":"10.1109/DRC.2006.305173","DOIUrl":"https://doi.org/10.1109/DRC.2006.305173","url":null,"abstract":"For the first time, we have demonstrated the feasibility of charge trap-based devices with ultra-thin tunnel oxide for high density DRAM application. Experimental results using direct tunneling scheme show good memory characteristics such as long retention time (>1000sec), large memory window (>1V), non-destructive read, high endurance, and acceptable programming speed (~100ns). Further improvement for low operation voltage and sub-6F2 cell size can be achieved by adopting a novel hot electron injection method. This novel operation scheme is helpful for efficient programming and minimizing disturbance. Due to the simple and fully logic compatible process, charge trap DRAM is considered to be a good candidate for future high-density DRAM and SOC applications","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130816591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Dynamic On-Resistance Kilovolt-Range AlGaN/GaN HFETs","authors":"N. Tipirneni, A. Koudymov, V. Adivarahan, J. Yang, G. Simin, M. Khan","doi":"10.1109/DRC.2006.305142","DOIUrl":"https://doi.org/10.1109/DRC.2006.305142","url":null,"abstract":"In the recent years, AlGaN/GaN Heterostructure Field Effect Transistors (HFETs) have been recognized as promising novel building blocks for power conversion and switching applications. The key challenge in high-voltage switching devices is to achieving high breakdown voltage VBR and low on-resistance RON simultaneously. For lateral devices, the RON minimization translates into achieving a given VBR with a minimal gate drain spacing LGD. In most of the reported AlGaN/GaN HFET switches, the field-plated design was implemented to achieve high breakdown voltages [1, 2]. In this paper we demonstrate that high VBR values, above 1 kV, can be achieved without field-plating; we for the first time show that the essential role of the field-plate in high-voltage AlGaN/GaN switches is to suppress the excessive gate leakage currents arising from the SiN passivation. This is the first report of an AlGaN/GaN HFET with the dynamic RON as low as 4 mQ.cm2 at the breakdown voltage VBR= 1000 V. Commonly, the VBR-LGD dependencies for high-voltage AlGaN/GaN HFETs saturate at large LGD values limiting the achievable maximum breakdown voltages below 400 800 V. Recently, we have shown [3] that the saturation observed in the VBR-LGD curves for the unpassivated HFET is due to a surface flashover, not to a bulk breakdown. The suppression of the surface flashover leads to a linear VBRLGD dependence up to LGD 20 ptm resulting in the breakdown voltage of 1600V [3]. It was also shown that even that high VBR values were still limited by surface breakdown and not by the channel avalanche. These results imply that the field plate commonly used in the high-voltage fEIFET design is not required to achieve high breakdown voltage. Thus the role of field-plating in improving the performance of high-voltage high-power AlGaN-GaN HFET switches needs to be revised. In this paper, we present the first detailed study of the role of field plate on the performance of HFETs for high power switching. The fEIETs devices were fabricated over sapphire substrate. The wafer sheet resistance was around 350 Q, the threshold voltage, VT =-6V. The ohmic contacts were formed by Ti(200A)/Al(ioooA)/Ti(500A)/Au(1500A) as metal combination. These were annealed at 850 °C for 1 min. in a forming gas ambient. The source-gate spacing was 2 pim, gate drain spacing was varying from 4 to 16 ptm. After Au/Ni gate formation, the devices were tested for breakdown voltage in air ambience and in Flourinert® ambience. As expected the VBR-LGD dependence was linear yielding the VBR","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116101394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation of Silicon Nanowire Bio-sensors","authors":"P. Nair, M. Alam","doi":"10.1109/DRC.2006.305048","DOIUrl":"https://doi.org/10.1109/DRC.2006.305048","url":null,"abstract":"To summarize the results, we find that (a) the sensitivity of a NW-sensor depends on device parameters in unexpected ways, (b) sensitivity is greatly affected by the presence of water, and (c) for bio-molecule detection, for maximum sensitivity, the pH should be so chosen that the NW is in depletion. Our simulation results demonstrates, for the first time, that it is possible to interpret the conductance modulation of nano-bio sensors in terms of specific molecule conjugations and to systematically optimize sensor response as a function of sensor geometry and fluidic conditions.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125259627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}