Low Dynamic On-Resistance Kilovolt-Range AlGaN/GaN HFETs

Abstract

In the recent years, AlGaN/GaN Heterostructure Field Effect Transistors (HFETs) have been recognized as promising novel building blocks for power conversion and switching applications. The key challenge in high-voltage switching devices is to achieving high breakdown voltage VBR and low on-resistance RON simultaneously. For lateral devices, the RON minimization translates into achieving a given VBR with a minimal gate drain spacing LGD. In most of the reported AlGaN/GaN HFET switches, the field-plated design was implemented to achieve high breakdown voltages [1, 2]. In this paper we demonstrate that high VBR values, above 1 kV, can be achieved without field-plating; we for the first time show that the essential role of the field-plate in high-voltage AlGaN/GaN switches is to suppress the excessive gate leakage currents arising from the SiN passivation. This is the first report of an AlGaN/GaN HFET with the dynamic RON as low as 4 mQ.cm2 at the breakdown voltage VBR= 1000 V. Commonly, the VBR-LGD dependencies for high-voltage AlGaN/GaN HFETs saturate at large LGD values limiting the achievable maximum breakdown voltages below 400 800 V. Recently, we have shown [3] that the saturation observed in the VBR-LGD curves for the unpassivated HFET is due to a surface flashover, not to a bulk breakdown. The suppression of the surface flashover leads to a linear VBRLGD dependence up to LGD 20 ptm resulting in the breakdown voltage of 1600V [3]. It was also shown that even that high VBR values were still limited by surface breakdown and not by the channel avalanche. These results imply that the field plate commonly used in the high-voltage fEIFET design is not required to achieve high breakdown voltage. Thus the role of field-plating in improving the performance of high-voltage high-power AlGaN-GaN HFET switches needs to be revised. In this paper, we present the first detailed study of the role of field plate on the performance of HFETs for high power switching. The fEIETs devices were fabricated over sapphire substrate. The wafer sheet resistance was around 350 Q, the threshold voltage, VT =-6V. The ohmic contacts were formed by Ti(200A)/Al(ioooA)/Ti(500A)/Au(1500A) as metal combination. These were annealed at 850 °C for 1 min. in a forming gas ambient. The source-gate spacing was 2 pim, gate drain spacing was varying from 4 to 16 ptm. After Au/Ni gate formation, the devices were tested for breakdown voltage in air ambience and in Flourinert® ambience. As expected the VBR-LGD dependence was linear yielding the VBR