2006 64th Device Research Conference最新文献_第7页

250 nm InGaAs/InP DHBTs w/650 GHz /spl conint/max and 420 GHz /spl conint/τ, operating above 30 mW/μm2 250 nm InGaAs/InP dhbt w/650 GHz /spl conint/max和420 GHz /spl conint/τ，工作功率大于30 mW/μm2

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305190

E. Lind, Z. Griffith, M. Rodwell, X. Fang, D. Loubychev, Yuehua Wu, J. Fastenau, Amy K. Liu

{"title":"250 nm InGaAs/InP DHBTs w/650 GHz /spl conint/max and 420 GHz /spl conint/τ, operating above 30 mW/μm2","authors":"E. Lind, Z. Griffith, M. Rodwell, X. Fang, D. Loubychev, Yuehua Wu, J. Fastenau, Amy K. Liu","doi":"10.1109/DRC.2006.305190","DOIUrl":"https://doi.org/10.1109/DRC.2006.305190","url":null,"abstract":"We report a 250 nm InP/In0.53Ga0.47As/InP double heterostructure bipolar transistor (DHBT), exhibiting a record 650 GHZfmax with simultanseous 420 GHzf,. This is to our knowledge the highestfmax reported for a DHBT. The emitter junction width has been scaled to 250 nm, substantial improvement has been made to the base and emitter Ohmic contacts, and the InGaAs subcollector has been thinned to increase the HBT thermal conductivity. The devices show excellent power handling, operating at power densities in excess of 30 mW/ tm2. Critically, unlike many previously reported DHBTs, the high power density associated with the devices here permits the HBTs to be biased simultaneously at high bias voltages and high current densities Je; an attribute as important as the breakdown voltage in determining the useful voltage capability of a transistor technology. Previous 0.6 ptm emitter InP DHBTs from UCSB utilizing a 150 nm collector displayed a 390 GHzf, and 505 GHZfmax, at Je = 5.17 mA/ tm2 [1]. Prior to this work the highest reportedfmax DHBT was 519 GHz with simultaneous 252 GHzf, [2]. Development of high speed digital and mixed-signal systems having increased bandwidths requires improved HBT performance. For example, projected 160 Gb/s systems require > 400 GHzf/fmax, and low collector base capacitance (CcblIc < 0.5 ps) [3]. By lateral scaling at a fixed vertical geometry, substantial improvement off,rax can be achieved due to the reduced Ccb and Rbb [4]. For sub-mm-wave amplifiers, an HBT having high frnax, high breakdown voltages, as well as an ability to operate at high power densities is required. The DHBTs presented in this work were fabricated in an all-wet-etch, triple mesa process. All device features were defined by I-line stepper lithography. An SEM of a completed device is shown in figure 1. The epitaxial material (Table 1) was grown by IQE Inc. The InGaAs base is 30-nm thick employing graded carbon doping from 7-4xl019 cm-3 that in-turn introduces AE, _ 50 meV of conduction band grading. To suppress any current blocking effects originating from the conduction band discontinuity between the InGaAs base and InP collector (AEC 0.26 eV), the collector utilizes a 15-nm InGaAs setback layer followed by a 24-nm InAlAs/InGaAs chirped super-lattice grade and appropriate pulse-doping so as to provide a continuous conduction band between Ino053Ga047As and InP. The emitter contact metal is 390 nm wide and SEM inspection shows 70 nm of lateral undercut during the mesa formation, making the emitter-base junction width 250 nm. To eliminate Cch underneath the base pad, the semiconductor associated with this area is etched away. The devices are passivated with and planarized using benzocyclobutene BCB. Transmission line measurements (TLM) show a base contact resistance Pc < 5 Q im2 and a base sheet resistance p, = 630 Q, and the collector Pc = 11 Q. m2 and p, = 12.5 Q. The emitter Pc = 5.3 Q. m2 was extracted from RF-parameter fitting. Compared to [1], this i","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115691576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Terahertz Emission of Radiation from InGaP/InGaAs/GaAs Grating-Bicoupled Plasmon-Resonant Photomixer InGaP/InGaAs/GaAs光栅-双耦合等离子体共振光度计的太赫兹辐射

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305052

T. Otsuji, M. Hanabe, Y. Meziani, E. Sano

引用次数: 1

Synthetic Nanomaterials for Novel Electronic Concepts 新电子概念的合成纳米材料

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305181

A. Javey

引用次数: 0

Buried-channel In0.70Ga0.30As/In0.52Al0.48As MOS capacitors and transistors with HfO2 gate dielectrics 埋道In0.70Ga0.30As/In0.52Al0.48As MOS电容器和HfO2栅极电介质晶体管

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305114

Yanning Sun, S. Koester, E. Kiewra, K. Fogel, D. Sadana, D. Webb, J. Fompeyrine, J. Locquet, M. Sousa, R. Germann

引用次数: 6

High-Performance GaAs MISFETs with Self-Assembled Nanodielectrics 自组装纳米电介质的高性能GaAs misfet

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305113

H. Lin, G. Lu, P. Ye, Y. Xuan, A. Facchetti, T. Marks

引用次数: 0

Measurement of Minority Carrier Diffusion Lengths in Semiconductor Nanowires 半导体纳米线中少数载流子扩散长度的测量

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305186

Jonathan E. Allen, Y. Gu, J. Romankiewicz, J. Lensch, S. May, Teri Odom, B. Wessels, L. Lauhon

引用次数: 1

Improved processing technology for GaN-capped deeply-recessed GaN HEMTs without surface passivation 无表面钝化的氮化镓封顶深凹槽hemt的改进加工技术

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305138

L. Shen, L. McCarthy, T. Palacios, M. Wong, C. Poblenz, A. Corrion, S. Keller, S. Denbaars, J. Speck, U. Mishra

引用次数: 0

High Performance Carbon Nanotube Ring Oscillator 高性能碳纳米管环形振荡器

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305170

Zhihong Chen, J. Appenzeller, P. Solomon, Yu-Ming Lin, P. Avouris

{"title":"High Performance Carbon Nanotube Ring Oscillator","authors":"Zhihong Chen, J. Appenzeller, P. Solomon, Yu-Ming Lin, P. Avouris","doi":"10.1109/DRC.2006.305170","DOIUrl":"https://doi.org/10.1109/DRC.2006.305170","url":null,"abstract":"Owing to their excellent electrical properties, single wall carbon nanotubes are found to be one of the most promising candidates for post-CMOS applications. While the individual device geometry of single nanotube transistors has been improved over the last few years and results in dc characteristics which can outperform silicon devices, very few attempts have been carried out to probe the ac performance of carbon nanotubes. In this paper, we demonstrate a high performance ring oscillator based on one individual single wall carbon nanotube. This is up-todate the most sophisticated circuit implemented on a single molecule and provides the potential to probe the intrinsic switching speed of carbon nanotubes. The frequency performance of our ring oscillator has been improved by 5-6 orders of magnitude, compared with previous ring oscillators fabricated on multiple nanotubes.\"12 As shown in fig. 1, we have fabricated a 5-stage CMOS ring oscillator entirely wired up on one single wall carbon nanotube. The nanotube was CVD grown on 100nm SiO2 substrate with -2nm diameter and 18ptm in length. Palladium source/drain contacts were defined on top of the nanotube, followed by the deposition of an A1203 gate dielectric and metal gate on top of each transistor channel. The 5-stage CMOS ring oscillator consists of 5 p-type FETs and 5 n-type FETs. The circuit layout is designed such that the same type FETs from contiguous inverter stages share the same source/drain contacts, which makes the circuit rather compact. To avoid any interference from the measurement set-up, we added an identical CMOS inverter stage right next to the ring oscillator and its output is directed to a spectrum analyzer. The complete circuit, including the aforementioned 6 inverter stages, is 9pm in width along the nanotube length. One more inverter stage is fabricated on the same nanotube to investigate the electrical properties of the nanotube such that the ideal parameter set for the ring oscillator measurement can be determined beforehand. In order to realize the CMOS scheme on a single carbon nanotube, we used different work function metal gates, i.e. palladium (Pd) for the p-FET and aluminum (Al) for the n-FET. The FET output characteristics obtained from the test inverter are shown in fig.2. To simplify the process, we used Pd for the source/drain contacts for both pand n-FETs. The p-FET shows small contact resistance at small drain voltages and decent saturation currents at high drain biases. In comparison, the n-FET carries much smaller currents at small voltages due to the same Pd source/drain contacts which favor hole carrier injection. However, at high drain bias the n-FET reaches similar high current levels as the p-FET, which is one of the key factors in ensuring a high oscillation frequency. The threshold voltages, Vth=-0.4V for the p-FET and Vth=OV for the n-FET, are successfully controlled by our work function scheme of the metal gates. In addition to these metal gates, we","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"517 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124478409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

InAsP/InAs Nanowire Heterostructure Field Effect Transistors 纳米线异质结构场效应晶体管

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305171

E. Lind, L. Wernersson

引用次数: 1

40-W/mm Double Field-plated GaN HEMTs 40w /mm双场镀氮化镓hemt

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI: 10.1109/DRC.2006.305162

YiFeng Wu, M. Moore, A. Saxler, T. Wisleder, P. Parikh

{"title":"40-W/mm Double Field-plated GaN HEMTs","authors":"YiFeng Wu, M. Moore, A. Saxler, T. Wisleder, P. Parikh","doi":"10.1109/DRC.2006.305162","DOIUrl":"https://doi.org/10.1109/DRC.2006.305162","url":null,"abstract":"Field plate technologies have dramatically raised the benchmarks of GaN-based high-electron-mobility transistors (HEMTs). Greater than 30 W/mm power density was demonstrated with gate-connected field plates'. The drawback of additional feedback capacitances added by the field plates was then addressed using source-termination, achieving 21dB large-signal gain and 20-W/mm power density at 4 GHz\"l. Recently, multiple field plates were pursued for further improvements\"\"v I. Here we present double field-plated GaN HEMTs with increased power density and robustness. The devices in this study consisted of a Cree HPSI SiC substrate, a 2-4 ptm thick insulating GaN buffer, a thin AlN interlayer and an Al0.26Gao.74N barrier layer. The GaN buffer was doped with Fe for enhanced resistivity and the AlN interlay was included to achieve a high charge-mobility product without the complication of increasing the Al mole fraction of the top AlGaN layer. The device has a first field plate (FP1) integrated with the gate for both reduced gate resistance and elimination of electron trapping. The task of further tailoring the electric field and attaining a higher breakdown voltage is accomplished by a second field plate (FP2), placed on the drain side of the first field plate. FP2 is electrically connected to the source of the HEMT to minimize feedback capacitance. When designed properly, the double field-plated devices can offer a more optimal electric field distribution, improving performance and robustness. Targeting high-power operation at C band, the length of FP1 was set at LF1=0.3-0.5 ptm and FP2 at LF2=0.9-1.2 ptm. The SiN dielectric thickness under FP1 and FP2 was 100 nm and 200 nm, respectively. The device fabrication steps were similar to previous reports,\"\" except for the gate formation, where the integrated gate and FP1 were deposited on the SiN layer with a previously etched gate opening. Devices of four configurations were fabricated for a direct comparison. Device A had no field plate. Device B had double field plates, both connected to the gate. Device C had double field plates, FP, connected to the gate and FP2 connected to the source. Device D had a single field plate connected to the source. The gate length was about 0.55 ptm and gate-drain separation was 3.5 ptm. Typical devices showed -4 V pinch-off voltage and >1.2 A/mm full channel current. While circuit element extraction from S-parameters revealed practically the same current gain cut-off frequency of 30-35 GHz for the intrinsic devices, the maximum stable gains (MSG) varied based on the extrinsic parasitics. In particular, with LF1=0.3 pim and LF2=0.9 pim, MSG values at 10-GHz and 41 V for devices A, B, C and D were 15.6 dB, 11.2 dB, 16.7 dB and 17.1dB, respectively. It is expected that device B with both field plates connected to the gate has a high feedback capacitance, hence a much lower MSG than the non-field-pate device A. With FP2 connected to the source, however, device C actually exhibi","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124560252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 336