Process development for the realization of thermally-reliable enhancement-mode InAlAs/InGaAs/InP HEMTs with excellent DC and RF performance

Ohmic contact degradation and gate sinking (especially when Pt is used as the gate contact for E-HEMTs) are two of the major reliability concerns for the InAlAs/InGaAs/InP HEMTs [1, 2]. Thermally-stable Ohmic contacts based on Ge/Ag/Ni metallizations have recently been developed [3]. They are annealed at temperatures higher than those used for conventionally annealed-AuGe/Ni/Au ohmic contacts. Schottky contacts based on Iridium have been shown to have barrier heights as high as Platinum-based Schottky contacts [4]. E-HEMTs fabricated utilizing Ir-gate have demonstrated better thermal stability than Pt-gate E-HEMTs [4]. Using FATFETs and C-V measurements, it was demonstrated that no gate diffusion occurred in thermally-treated Ir-gate E-HEMTs whereas there was gate diffusion in Pt-gate devices [4]. In this work, we have combined the Ir-gate contact and Ge/Ag/Ni-ohmic contact technologies to fabricate high performance E-HEMTs with high thermal stability potential. The heterostructure used for this study was grown by molecular beam epitaxy on (100) semi-insulating InP substrate. The schematic is shown in Fig. 1. The sheet resistance, sheet carrier concentration, and electron mobility, as determined by Hall measurements, were 253 Q/z, 2.97 x 1012 cm-2 and 8295 cm2/V-S, respectively. Ohmic contact optimization process based on transmission line method (TLM) with metallization of Ge/Ag/Ni was first performed to determine the optimum annealing conditions for ohmic formation. Also, Schottky diodes using Ir/Ti/Pt/Au contact metallization were fabricated to study Schottky barrier height enhancement as a function of annealing temperature. Both the TLM samples and Schottky diodes were passivated using a 60-nm-thick SiNX layer prior to annealing in a rapid thermal annealing (RTA) system for 30 seconds. Device fabrication starts with mesa and sidewall isolations using a mixture of citric acid and hydrogen peroxide. The metallization of Ge/Ag/Ni was then deposited using electron beam evaporation and lift-off techniques for ohmic contact. T-shaped gate was defined by e-beam lithography system. The following recess procedure was performed after the gate definition: the 8-nm-thick Ino.53Ga047As contact layer and 6-nm-thick undoped In0o52A10o48As layer was first selectively removed using a citric acid/hydrogen peroxide solution. Then the first AlAs etch stop layer was removed by a solution of HCl and DI water in the ratio of 1: 2. Using the same solution of citric acid, the 3.5-nm-thick undoped Ino52A1048As D-HEMT barrier layer was subsequently removed followed by the removal of the second layer of AlAs etch stop by the same HCl solution that was used for the first AlAs layer. After the gate recess, Ir/Ti/Pt/Au were evaporated by e-beam evaporator. Before the ohmic and gate contacts were annealed simultaneously, a SiNX layer was deposited by PECVD. This SiNx layer also acted as the passivation layer for the final device. The sample was annealed at 425 °C for 30 seconds in a rapid thermal annealing (RTA) system. After annealing, an overlay metal stack of Ti/Pt/Au was deposited. The gate width and source-drain spacing of the devices were 100 ptm and 2 ptm, respectively Figure 2 shows a minimum contact resistance of 0.1 Q-mm at an annealing temperature of 425 'C. Figure 3 shows that Schottky diodes based on Ir/Ti/Pt/Au metallization on nW-InAlAs yielded the highest barrier height at 824 meV when it was annealed at 400 'C. At an annealing temperature of 425 'C, the barrier height was 820 meV. Figure 4 shows the forward current and ideality factor of the Schottky diode that was thermally-treated at 425 'C. Based on these results, a simultaneous thermal treatment for the Schottky gate and ohmic contact at 425 'C for 30 sec was adopted for device fabrication. E-HEMTs with gate-lengths of 0.1 ptm and 0.25 ptm were fabricated. Excellent DC and RF characteristics for the 0.1 ptm gate-length device are shown in Figs. 5 and 6, with VT of 198 mV, Gm,max of 945 mS/mm, ID,maxof 435 mA/mm (drain current at VG = 0.7 V, VD = 1.OV), IDSS of 0.25 mA/mm (drain current at VG= 0 V, VD= 1.0 V), andfT of 205 GHz. The threshold voltage andfT for the device with a gate-length of 0.25 ptm were 259 mV and 86 GHz, respectively. In conclusion, we have developed a novel fabrication process for E-HEMTs based on Ir-gate and Ge/Ag/Niohmic contact technologies. In addition to excellent DC and RF performances, these E-HEMTs are expected to be highly thermally stable. Results on thermal stability will be presented. These metallization have also been applied to depletion-mode with excellent results. References [1] J. A. Del Alamo et al.. IEDM Tech. Dig, pp. 44.1.1, Dec. 2004. [2] M. Dammann et al,AMicroelectronics Reliability, 44, pp. 939, 2004 [3] W. Zhao et at., Electron Dev. Lett. 27, pp.4, 2006 [4] S. Kim et al., DRC Dig., pp. 259, 2005.