The new Shielded Bitline Sensing Method for FC-SGT Flash memory

Abstract

In this paper, we propose a new Shielded Bitline Sensing Method for Floating Channel Surrounding Gate Transistor (FC-SGT) Flash memory [1], which enable to suppress a bitline capacitance coupling noise without reducing its read throughput. The new shielding method is accomplished by the 3-D structure ofthe FC-SGT Flash memory and its high flexibility ofwiring. We illustrate a structure of the FC-SGT Flash memory cell in Fig.1 [1]. A channel region, whose shape is a pillar, is surrounded by a tunnel oxide, floating gate, inter-poly insulator, and control gate. A drain and source electrode are located at the end ofthe silicon pillar. All bitlines run parallel to sourcelines. The writing and erasing operation work with FN tunneling. Due to these own features, the FC-SGT Flash memory is suitable for the low-power operation and high density storage To operate a read sequence with the open bitline architecture, the bitline coupling capacitance generates a large bitline capacitance coupling noise. As shown in Fig.2, when nearest bitlines from a bitline are discharged, the bitline capacitance coupling noise A VNlbecomes the worst value, which is expressed by the Eql. Reading the FCSGT Flash memory cell with conventional open bitline architecture, we now calculate the bitline capacitance coupling noise. According to ITRS 2005's parameters [2] and plate capacitance assumption (see Fig.3), we can calculate that the bitline coupling noises becomes Eq2. IfVpc equal 1.8V, the charged bittlines are discharged from 1.8V to 0.83V. So, it is difficult to read the content ofthe operated cell. And the more dense memory cells become, the larger bitline capacitance coupling noise become. In order to solve this problem, the Shielded Bitline Sensing Method has been proposed [3]. Fig.4 shows the equivalent circuitry of the Shielded Bitline Sensing Method. It is that the pre-charge voltage Vpc is applied to every second bitlines, while left of bitlines are connected to the GND. Then we obtain the suppressed noise value A VN3X which is given by Eq3. The Cbitl is very smaller than the Cbit2, so we can almost neglect the bitline capacitance coupling noise. In case ofthe conventional shielded bitline sensing method, we can not operate all bitlines simultaneously. So as to read all bitlines at the same time, we propose novel Shielded Bitline Sensing Method for FC-SGT Flash memory. We describe the memory cell array ofthe FC-SGT Flash memory in Fig.5. The new shielding scheme is realized by its 3-D structure and unique memory cell array. The equivalent circuit and bird's eye view of the memory cell, which use new Shielded Bitline Sensing Method for FC-SGT Flash memory, are illustrated as Fig.6 (a) and (b) respectably. Fig.6 (a) and (b) show the same condition. The bitline and sourceline is located by tumns. It is that the pre-charge voltage Vpc is applied to bitlines. In the other hands, sourcelines are connected to the GND. Hence the voltage difference between a bitline and its nearest sourcelines always equal Vpc, as shown in Fig.6 (a). Thus the bitline coupling noise is eliminated, and we can read all bitlines at the same time.