Accumulated Body MOSFET

Multi-gate MOSFET structures have been investigated in recent years for increased electrostatic control of the channel potential and electrostatic threshold voltage tunability. Multi-gate transistors typically have two parallel gates straddling the device body [1]. We have integrated additional side-gates to planar nMOSFETs fabricated on bulk Si platform using Si3N4 shallow trench isolation (STI) with 19 nm Si3N4 side-gate insulator, and 4 nm thermally grown SiO2 top-gate insulator (Fig. 1). The side-gate surrounds the active area such as a guard ring, and the top-gate is independently controlled [2]. The side-gates of the device are used to accumulate the side-interfaces with application of a negative bias, while the top-gate is used for transistor operation as in a conventional FET. Accumulation of the holes at the periphery results in significant reduction in defect assisted recombination current from drain to substrate at the side interfaces (Fig.2), thus increased defect tolerance and reliability for strained Si technologies [3]. As the device width is reduced, the side interfaces draw near, countering the depletion effects. This results in accumulation of the device body for narrow channel devices (Fig. Id). The narrow channel devices exhibit distinctly different characteristics depending on the channel width and the amount the side-gates are recessed below the level of active area (Fig. ib), resembling tri-gate FET [3], as opposed to being at the same level (Fig.Ic). The accumulation of the side-interfaces suppresses the peripheral Ids leakage along the Si-STI interfaces and eliminate the need for edge implants [5] while resulting in excellent characteristics, such as an lo,/Ioff > 6 x 1010 for aW x L = 0.6 pim x 0.3 pim device (Fig. 3,4). As the width of the device is reduced close to the depletion depth (Wd) in the channel region, the source, drain junction depletion are reduced, as well as depletion region under the gate. This results in suppression of leakage currents due to punch through and drain induced barrier lowering (DIBL) for short channel devices as a function Of VSid, (Fig. 5-8). The physical gate length of this device is estimated to be 69 nm from SEM and effective width (Weff) is estimated to be 150 nm from its C-V characteristics, indicating significant side-gate recess given that W,= 79 nm. Maximum drive current of this device exceeds 1.6 mA/ Im Weff. The effective mobility (4etff) calculated for a Weff= 23 nm, Leff 140 nm device is below 100 cm2 V-s (Fig. 9), however, the maximum saturation transconductance, gm = 0.74 mANV.im, result in an estimated electron saturation velocity of 8.6 x 106 cm/s [6]. At these device dimensions DIBL is suppressed below 10 mVNV. Planar accumulated body FETs with Weff < 10 nm exhibit extreme Vt response to VSid, (Fig. 10). Vt can be tuned from 1 V to 4 V within the -0.5 V < VSid, < -2 V range with sensitivity, Y = V/6Vside > -2.1 V/V in the -0.5 > Vside > -1 V regime. The threshold voltage sensitivity (y) follow a parabolic trend, saturating at large values of -Vside. To the best of our knowledge, the electrostatic Vt tunability observed in this structure is more than 2 times what has been reported for back-gated MOSFETs [1]. No DIBL is observed at this device width. The side-gated bulk Si MOSFET design allows integration of narrow channel Vt tunable and low leakage accumulated body FETs with wider devices required for larger current drives on the same platform. High drive, low leakage currents are achieved with narrow channel devices at sub-70 nm gate length. The accumulated body FET, with strong control of the body potential, is a good candidate for further scaling of gate length ofMOSFETs while achieving very low level of leakage currents.