Numerical Simulation of Field-Induced Inter-Band Tunneling Effect Transistor Using TCAD-Based Device Simulator

Abstract

The field-induced inter-band tunneling effect transistor FITET is a practical quantum-tunneling device based on an SOI CMOS structure having both negative-differential transconductace (NDT) and negative-differential conductance (NDC) characteristics [1-3]. For the efficient simulation of these devices, exploiting band-to-band tunneling (BTBT) effects, we have previously developed numerical forward BTBT model and obtained NDC simulation results in 2-terminal silicon tunnel diodes [4]. In this paper, we performed the numerical simulation and device engineering for 3-terminal FITET structure by exploiting calibrated parameters from the forward BTBT model [4] in the commercial device simulator DESSIS [5]. Fig. 1 shows the numerical simulation results of transfer IV characteristics for the SOI CMOS structure with LG= 130 nm, tox= 3 nm, and tsoi= 40 nm. We designed long channel device to get rid of secondary parasitic effects such as short channel effects and gate tunneling. In the new local BTBT model for a body doping concentration of 1x1020/cm3, NDT characteristics are successfully simulated as in the previous experimental data [1,2], while the conventional BTBT model [6] cannot describe the observed NDT characteristics. In Fig. 2(a), we confirm the maximum band alignment between source and body in n-FITET case when VGS is 2.8 V, which is the peak voltage in the NDT curve of Fig. 1. Then, the forward BTBT in the source-to-body junction is suppressed as the body potential increases (band and quasi-fermi energy decreases) due to the injection of the excess hole carriers into the p+-doped floating body through reverse BTBT in the drain-to-body tunnel junction (Fig. 2 (b)). In the simulation of output I-V characteristics for the n-FITET (Fig. 3(a)), the NDC curve at VGS= 2.8 V also has been obtained and two output curves at VGS= 2.8 V and VGS= 3.2 V cross as in the experimental results ofp-FITET of Fig. 3(b) [3]. As shown in Fig. 4(a), BTBT current can be generated between the forward tunnel junction on the source side to the reverse tunnel junction of the drain side through the energy band alignment since the body potential decreases when VGS is 2.8 V where maximum depletion occurred in the body region. For a higher gate voltage of 3.4 V, the body potential increases due to the injection of the excess hole carriers in the floating body due to the increased reverse field between drain and gate, and then the BTBT current is suppressed at the same drain bias VDS= 0.1 V (Fig. 4(b)). The gate field effect on the tunnel junction plays a key role in the NDT/NDC characteristics of FITET. Figure 5, which shows a 2-dimensional contour plot of the electric field at VGS= 2.8 V, indicates that a strong electric field has been generated by the gate field, especially at the region between the junction and gate oxide interface where lateral (x-direction) junction and perpendicular gate field (y-direction) are superposed. We observed the BTBT rate with a maximum value at the same point as well as electric field shape with two peaks near source and drain tunnel junctions by cutting the contour plot along the x-direction at the surface (Fig. 6 (a)). The reverse BTBT rate at the drain side is much larger than the forward BTBT rate at the source side due to the drain field in addition to the tunnel junction and gate field. Fig. 6 (b) shows a plot of the extracted maximum BTBT rate at each gate voltage for source and drain tunnel junctions, respectively. In the NDT region, both forward and reverse BTBT rates decrease according to the movement of the energy band alignment as shown in Fig. 2. Fig. 7 shows the simulation results of transfer IV characteristics as a function of AL, which determines if it is an underlapped or overlapped gate structure. It can be noted that NDT characteristics disappear when AL is over 5nm. Therefore, the gate field should have an effect on the tunnel junction for NDT and the overlapped structure with ultra-thin source/drain tunnel junction on SOI CMOS structure is one of the prerequisites for the FITET fabrication yield. Fig. 8 and Fig. 9 show the simulation results of transfer IV characteristics and output IV characteristics for n-FITET with SOI thickness tsoi of 40 nm and 5 nm, respectively. From these results, we conclude that the surface region under the gate plays a dominant role for NDT and NDC characteristics of FITET. Using the proposed forward BTBT model parameters, the simulation of both NDT and NDC characteristics in the FITET has been successfully performed with a device simulator. We confirm the operation principle ofFITET by simulation and have investigated gate field effects on the tunnel junction through the efficient device engineering on a standard TCAD platform. Acknowledgements: This work was supported by the MARCO MSD center. Refs.: [1] K. R. Kim et. al, IEEE Electron Devices, 23 612 (2002) [4] K. R. Kim et. al, 2005 IEEE SISPAD Proc. pp. 159 162 [2] K. R. Kim et. al, IEEE Electron Devices, 25 439 (2004) [5] DESSISTM, Synopsys-ISE TCAD Release 10.0 [3] K. R. Kim et. al, 2004 62nd DRC proc., pp. 217 218 [6] E. 0. Kane, J. Phys. Chem. Solids, 12 181 (1959)