50 nm AlGaN/GaN HEMT Technology for mm-wave Applications

Abstract

AlGaN/GaN high electron mobility transistors (HEMTs) have shown in the last few years an important increase in their high frequency performance, both at small and large signal levels. In 2005, Higashiwaki et al. and then Palacios et al. demonstrated a maximum current gain cut-off frequency of 163 GHz in unpassivated devices with a gate length of 60 and 90 nm respectively. Shortly after, Palacios et al. used a sacrificial Ge layer to reduce the parasitic capacitances and demonstrate a maximum fT of 153 GHz and an fmax of 185 GHz in passivated devices with Lg 90 nm. Recent output power measurements in excess of 10 W/mm at 40 GHz have demonstrated the tremendous potential of this material system for power amplification at mm-wave frequencies. All these results have motivated a high interest to expand the operating frequency of GaN-based transistors above 94 GHz. To get these very high operating frequencies, devices with extremely short gate lengths are necessary. This paper demonstrates a new deep submicron AlGaN/GaN technology based on the use of dielectric sidewalls to reduce the gate length of these devices down to 50 nm. All the samples used in this work were grown by metalorganic chemical vapor deposition (MOCVD) on SiC substrates. The sample structure consisted on a GaN buffer layer, followed by a 1 nm InO 1Ga0o9N backbarrier, 5 nm GaN channel, 0.6 nm AlN interlayer and 25 nm AlO 32Ga0 68N cap layer. During the processing of the devices, a metal stack of Ti/Al/Ni/Au was used for the ohmic contacts and annealed at 870°C for 30 s. Then, mesa isolation was performed with a C12-based reactive ion etching. The sample was passivated with a PECVD SiN layer. To reduce the parasitic gate capacitances in the deep submicron gates, a Ge sacrificial layer was deposited on top of the SiN passivation. After the Ge evaporation, the sample is coated with a ZEON ZEP-520 e-beam resist layer and the ebeam lithography of the foot of the gate is performed. During this lithography, gate structures with lengths in the 100-150 nm range were defined. A two-step dry etch process based on CHF3/CF4/02 plasmas was used to transfer the gate foot to the Ge and SiN layers. To shrink the gate lengths of these devices even further, a SiN layer was deposited conformably by PECVD. The SiN sidewalls deposited in this way reduced the gate length down to 50 nm. A CF4/02 plasma was used to remove the SiN from the top of the Ge sacrificial layer and from the bottom of the gate foot. This etch step is critical to assure a good gate morphology. Early attempts to develop a deep submicron sidewall technology had the problem of how to fill up the foot of the gate with the metal. In our novel approach, we use the higher etch rate of SiN against Ge to reduce the height of the SiN sidewall with respect to the top of the Ge sacrificial layer. As shown in Figure 1, this difference in height will allow the successful metallization of the gate. The top of the gate is defined by a second e-beam lithography and a Ni/AulNi metal stack was deposited as gate metal. Finally, the Ge sacrificial layer was etched away in hot H202. Figure 2 shows an electron micrograph of the final gate structure. The devices with 50 nm gate length showed a very high current density in excess of 1.7 A/mm (Figure 3). As shown in Figure 4, there is an important increase in the total current for gate lengths shorter than 70 nm. Although further studies are necessary, this increase in the total current may be due to the onset of velocity overshoot effects in GaN. From theoretical studies these effects should be apparent for gate lengths in the 20-50 nm range. This higher electron velocity could also explain the very high transconductance (gm) measured in these devices. Figure 5 shows the evolution of gm with VDS for different VGS values. A maximum extrinsic gm of 320 mS/mm was observed in the 50 nm devices. This value is very high for a transistor structure with 25 nm cap layer and it is almost 3000 higher than in devices with a gate length of 100 nm. Also, from Figure 5, the beneficial effect of the InGaN back-barrier is evident in the good pinch-off of the device, independently of the drain voltage. The destructive breakdown voltage of these deep-submicron devices was in excess of 40 V. In conclusion, in this paper we have presented a novel 50 nm technology for GaN-based devices which combines a Ge-spacer sacrificial layer with SiN sidewalls to shrink the gate in a highly reproducible fashion. From the preliminary study of these 50 nm devices, an important increase in maximum drain current and transconductance is evident, which may be due to the onset of velocity overshoot effects at these very short dimensions. High frequency small-signal measurements and a detailed study of the electron velocity in these devices will be performed.