低接触电阻的低成本应变硅SRAM技术

2006 64th Device Research Conference Pub Date : 2006-06-26 DOI:10.1109/DRC.2006.305174

I. Polishchuk, S. Levy, R. Kapre, O. Pohland, K. Ramkumar, Nirav R. Shah, S. Thompson

{"title":"低接触电阻的低成本应变硅SRAM技术","authors":"I. Polishchuk, S. Levy, R. Kapre, O. Pohland, K. Ramkumar, Nirav R. Shah, S. Thompson","doi":"10.1109/DRC.2006.305174","DOIUrl":null,"url":null,"abstract":"This paper presents a simple and cost-effective method to enhance 65nm SRAM technology performance using a single stress liner, resulting in 25% increase in cell read current. A novel slot contact process allows significant improvement of NMOS drive current without PMOS degradation, by relaxing the undesirable strain in the PMOS. This new slot process also results in significant reduction of the S/D contact resistance.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"146 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Low-Cost Strained Silicon SRAM Technology with Reduced Contact Resistance\",\"authors\":\"I. Polishchuk, S. Levy, R. Kapre, O. Pohland, K. Ramkumar, Nirav R. Shah, S. Thompson\",\"doi\":\"10.1109/DRC.2006.305174\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a simple and cost-effective method to enhance 65nm SRAM technology performance using a single stress liner, resulting in 25% increase in cell read current. A novel slot contact process allows significant improvement of NMOS drive current without PMOS degradation, by relaxing the undesirable strain in the PMOS. This new slot process also results in significant reduction of the S/D contact resistance.\",\"PeriodicalId\":259981,\"journal\":{\"name\":\"2006 64th Device Research Conference\",\"volume\":\"146 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 64th Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2006.305174\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 64th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2006.305174","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文提出了一种简单而经济的方法来提高65nm SRAM技术的性能，使用单个应力衬里，使电池读取电流增加25%。一种新颖的槽接触工艺，通过放松PMOS中的不良应变，可以显著提高NMOS驱动电流，而不会导致PMOS劣化。这种新的槽制程也显著降低了S/D接触电阻。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Low-Cost Strained Silicon SRAM Technology with Reduced Contact Resistance

This paper presents a simple and cost-effective method to enhance 65nm SRAM technology performance using a single stress liner, resulting in 25% increase in cell read current. A novel slot contact process allows significant improvement of NMOS drive current without PMOS degradation, by relaxing the undesirable strain in the PMOS. This new slot process also results in significant reduction of the S/D contact resistance.

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2006 64th Device Research Conference

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