SiC Nanocrystal Flash Memory Fabricated with Protein-mediated Assembly

As a potential candidate of future flash memory, flash memory with nanocrystal floating gate is getting more and more attention because of its high program/erase speed, long retention time and good scaling ability [1, 2]. However, one most important challenge for flash memory with nanocrystal floating gate is the size and distribution control of the nanocrystal. Selfassembly of nanocrystals with traditional methods, such as chemical vapor deposition (CVD) [3], cannot get uniform size and distribution even with surface pre-treatments. This will cause the variation of electronic characteristics for final memory devices. Protein has been demonstrated to be a good template to organize the nanocrystals on SiO2 surface based on our previous work [4]. In this paper, we will present our studies about flash memory with SiC nanocrystal fabricated with protein-mediated assembly. P-MOS capacitors with SiC nanocrystal floating gate on SiO2 were fabricated on n-type Si (100) substrate. The schematic structure is shown in Fig. 1. After thermal oxidation for tunnel oxide, the wafer was immersed in PTS (phenyltriethoxysilane) solution in order to pretreat the surface. Next, the wafer was floated on the chaperonin protein solution with the oxide side down. The chemical environment of each chaperonin's central cavity was used to trap a nanocrystal. Once nanocrystals were trapped by the chaperonin template, the template was removed by annealing in 02 at 2000C. The density of nanocrystals up to 1012/cm2 has been demonstrated. The thicknesses of tunnel oxide and control oxide are 4nm and 12nm, respectively. A clear hysteresis with around 1.7 V flatband voltage shift can be observed from the high frequency capacitance-voltage (HFCV) characteristics (Fig 2), which is a clear effect of the charge stored the nanocrystals. The gate voltage is swept from inversion to accumulation to get forward HFCV and from accumulation back to inversion to get reverse HFCV. Fig 3 shows the memory programming and erasing speed characteristics with +8V and 1IOV pulse. After program and erase, 0.3 V flatband voltage shift can be observed even if the pulse width is shrunk to 1 00ls. Because of the deep well created by SiC nanocrystals, the flash memory shows very good retention characteristics at both room temperature and 85°C (Fig 4). After excess charge loss in the initial step, the charge loss rate is as small as 0.005/decade at 85°C and a memory window larger than 1V will be obtained after 10 years. In the endurance measurement, after up to 105 program/erase cycles with I1OV lOms pulse, the memory window does not show obvious closure. We have experimentally demonstrated the significant advantages of the SiC nanocrystal floating gate with long retention and good endurance characteristics.