Exploring Low Temperature Poly-Si for Low Cost and Low Power Sub-micron Digital Operation

Abstract

In recent years, low power consumption at medium performance (10-1OOMHz) has become the primary design criteria for portable devices such as cellular phones, medical electronics etc. Fabrication of such digital circuits on flexible substrates will open plethora of applications integrating computational power in every walk of human life. Sub-micron silicon technologies are able to provide desired low-power and performance, however, fabrication requires large thermal budget making them unsuitable for flexible substrates. Flexible substrates limit the thermal budget to 500°C, inhibiting the fabrication of ultra-thin gate dielectrics. To reduce the fabrication costs, we explore amorphous (a) and low temperature polycrystalline (LTp) silicon thin-film transistors (TFTs) for digital circuits on flexible substrates. Conventionally, LTp-Si TFTs are used in active-matrix LCDs as pixel switching elements and integrated drivers because of their ease of fabrication on plastic substrates. Low thermal budget limits the grain size and gate dielectric thickness (To,) scaling. Small grain size reduces the carrier mobility because of traps at the grain boundaries (GBs) and non-scaled To, degrades the I-V characteristics, further degrading the performance. To improve the performance, grain size can be increased using Metal Induced Lateral Crystallization, Solid Phase Crystallization etc., however, it increases thermal budget and fabrication costs. Another option would be to scale the gate lengths of LTp-Si down to average grain size. However, reducing the gate lengths will require scaled gate dielectric increasing the thermal budget. We propose a methodology to optimize LTp-Si TFTs to improve performance while keeping short-channel-effect (SCE) under control along with low thermal budgetfor digital VLSI circuits onflexible substrates. For TFTs, first a-Si is deposited and then crystallized to increase the grain size. LTp-Si has average grain size of few hundred nanometers. LTp-Si TFTs can have longitudinal and latitudinal grain boundaries. With process control and careful layout, GBs in a channel can be restricted to longitudinal only. In p-Si, mobility is affected by the carrier trapping at the GB regions (Fig. 1). The carrier transport in good quality grains is similar to that of crystalline silicon (c-Si). The effective mobility can be given by [1]