The Impact of Strained Engineering for 65nm FUSI CMOSFETs

Abstract

Chieh-Ming Lail, Yean-Kuen Fang', Wen-Kuan Yeh2, Chien-Ting Lin 1. Institute of Microelectronics, National Cheng Kung University, Taiwan. 2. Department of Electrical Engineering, National University of Kaohsiung, Taiwan. No. 1 University Road, Tainan, TAIWAN, 70101, Tel: 886-6-2080398, FAX: +886-6-2345482 e-mail: ykfangAeembox.ee.ncku.edu.tw As the devices geometry is scaled down continually, some issues such as the boron penetration, poly gate depletion and low carrier mobility become more critical and serious. Metal gate is an efficient approach to eliminate the boron penetration and poly gate depletion [1], and fully silicided (FUSI) is a promising metal gate candidate due to the simplified processing as well as the tunable work function [2]. On the other hand, the high stress contact etch stop layer (CESL) has been used extensively to promote channel carrier mobility in conventional devices [3]. However, very few studies inspected the impact of high tensile stress CESL (TS CESL) on FUSI devices performance yet. In this work, we investigated the device driving capacity, leakages, low frequency noise (LF noise) and C-V characteristics for 65nm Ni-FUSI CMOSFETs with and without the TS CESL. Devices were fabricated using a modified standard CMOS process. After S/D Cobalt salicidation, the first TS CESL (700A) was deposited (Fig. 1(a): control device). After the inter layer dielectric oxide was deposited, FUSI CMP planarization was adopted to remove the I't TS CESL down to polysilicon gate. In this work, Ni-silicide has been used for the FUSI technology because of lower thermal budget and better properties [4]. Finally, the Ni-FUSI gate electrode was formed after RTP (Fig. 1(b)). In order to inspect the impact of high tensile stress in Ni-FUSI devices, some Ni-FUSI devices were deposited by TS CESL (700A) (Fig. 1(c)). Figure 2 shows the ID-VD curves for nMOSFETs with IVG-VTI=lV, it is found that devices with Ni-FUSI gate possess higher driving capacity than control devices do, which is due presumably to the better gate control under the same VG-VT; therefore, larger channel charges will be induced in channel region, lowering the channel resistance. Besides for these Ni-FUSI devices, the driving capacity can be also enhanced by a TS CESL. It implied that the TS CESL is an efficient method to improve driving capacity in Ni-FUSI devices. Fig. 3 shows that Ni-FUSI devices with TS CESL possess the highest Gm MAX. In Fig. 4, because of the positive shift of flatband voltage, the Ni-FUSI devices possess higher threshold voltage (VT) and better subthreshold swing especially for devices with TS CESL. In comparison with control device, the best noise performance was found in Ni-FUSI devices without TS CESL, as shown in Fig. 5. In Fig. 6, the Ni-FUSI devices without TS CESL possess lower junction leakages than the control devices does. For devices with Ni-FUSI gate, lower junction leakages was found, which is due presumably to the smoother band bending in Si/SiO2 interface happen, lowering the accumulated electrons in channel region. On the other hand, we believed that the RTP in FUSI process can also improve the integrity of S/D junctions. And the junction leakage in device with TS CESL is slightly high because of the tensile stress induced defect happen. The gate leakage is shown in Fig. 7, it found that there is no apparent difference between control devices and Ni-FUSI devices; it implied that the process of FUSI CMP didn't induce additional damages to gate oxide. From Fig. 6 and 7, we believed that the LF noise characteristic was mainly affected by junction leakage. In comparison with control device, lower poly gate depletion can be found on Ni-FUSI devices, as shown in Fig. 8. And larger accumulation capacitance is found on Ni-FUSI device without TS CESL because without TS CESL-induced defects happened. For pMOSFETs, the ID-VD curves were shown in Fig. 9. Similar to the nMOSFETs, those Ni-FUSI devices without TS CESL possess better driving capacity than the control devices does. But for Ni-FUSI device with TS CESL, lower driving current was found because the inappropriate TS CESL-induced tensile stress (should be compress not tensile) will degrade pMOSFET performance. Investigation from the characteristics ofGm (Fig. 10) and ID-VG (Fig. 11), we found that the TS CESL also caused worse Gm and the subthreshold characteristics (IOFF, SS). Similar tendency ofLF noise was found on pMOSFETs, as shown in Fig. 12. Compared to control device, the best one was happened on Ni-FUSI devices without TS CESL. We believed that the worst LF noise in control device is affected by larger junction leakages (Fig. 13), not by the gate leakages (Fig. 14). A C-V curve for pMOSFETs was shown in Fig. 15. Similar as nMOSFETs, Ni-FUSI pMOSFETs without TS CESL possess the larger accumulation capacitance. In this work, the driving capacity, leakages, low frequency noise (LF noise) and C-V characteristics were investigated for 65nm FUSI nand pMOSFETs with and without the TS CESL to inspect the impacts of TS CESL on FUSI devices performance. In nMOSFETs, a TS CESL will improve the driving capacity, but it also induced more defects and enlarged junction leakages, resulting in higher LF noise and decreasing the accumulation capacitance. In pMOSFETs, the TS CESL is profitless for device performance due to an inappropriate stress (should be compress not tensile). Furthermore, we also found that the FUSI process didn't caused apparent damages to the gate oxide for both Ni-FUSI nand pMOSFETs. The work is supported byUMC Device Engineering Division the National Science Council ofTaiwan, R.O.C., under Contract NSC 94-2215-E-006-005 and 94-2215-E-390-001. [1] B. Tavel et al., IEDMATech. Dig, pp.825 (2001) [2] C. Cabral et al., Symo. VLSI Tech., pp.184 (2004) [3] S. Pidin et al., Symo. VLSI Tech., pp.54 (2004) [4] Z. Krivokapic et al., IEDM Tech. Dig, pp.271 (2002)