Effect of Poly-Si Gate Depletion on Tuning Range in MOS Varactors

Abstract

High quality and high tuning range on chip varactors are needed for implementation of VCOs in the standard CMOS technologies for RF applications. Varactors are implemented as a reverse biased diode or as a MOS capacitor operating in accumulation-depletion region [1]. The MOS varactors are preferred due to their superior tuning range compared to the diode [2]. The tuning range in MOS varactor is governed by oxide capacitance (Cox) and the minimum silicon capacitance in depletion (Cdep min). Since the gate oxide thickness dictates the maximum capacitance in a MOS capacitor structure, further improvement in the tuning range can be achieved, if the minimum capacitance is decreased further. To improve the varactor tuning range, Poly-Silicon depletion effect is exploited [3]. Poly-Silicon depletion effect arises due to low doping in the Poly-Si and formation of depletion region in Poly-Si region. This in turn reduces the effective gate capacitance Cox and consequently the drive current. Poly-Si depletion effect, which is generally avoided in order to design high performance CMOS transistors, is introduced intentionally by exposing the gate electrode of MOS varactor to appropriate implant steps [3] (Figure 1). The n-type doping concentration in the Poly-Si gate at the Poly-Si/oxide interface is intentionally decreased (N-). When the p-type silicon substrate is in accumulation mode (for VG < VFB), the gate Poly-Si is also in accumulation mode and hence the total gate capacitance is essentially Cox. However during the depletion mode (for VG > VFB), if the doping concentration near the Poly-Si/SiO2 interface is less than about IxIO19 cm-3, then the Poly-Si region near the SiO2 interface is also depleted. It can be viewed as an addition of another series capacitance, Cp01y (Figure 1). So effective capacitance is series combination of three capacitors. Thus adding the poly-depletion effect reduces Cminimum. The varactor structure is simulated in an optimized 100nm CMOS process flow [4]. The baseline CMOS process flow utilized disposable spacer technique [5] to optimize the varactor (VI) performance. Instead of p+ Poly-Si, the varactor structure use n-type Poly-Si gate and p-type substrate with p+ deep source/drain implants for making the contacts. The different varactor structures V2, V3 and V4 are realized by defining appropriate boolean operations on Poly-Si masks for NMOS (PMOS) deep source/drain implant and NMOS (PMOS) extension/halo implants as shown in table I [3]. The maximum improvement in the tuning range, with respect to the reference device, is observed to be 60 00 in varactor V4 as shown in figure 2. For measuring the Q factor, the admittance matrix is calculated. The conductance between gate and other electrode for various cases is as shown in figure 3. It is observed that there is no significant change in the conductance value. So quality factor is not degraded. Poly-Si gate in varactor V4, which gives maximum tuning range, is exposed to NMOS halo and extension as well as PMOS halo and extension implants. The doping profile in Poly-Si is box shaped with entire low doping region getting depleted. Hence there is no change in the conductance value. Thus this technique improves the tuning range without degrading the Q factor. The tuning range improvement is a strong function ofN+ extension implant parameters. Deep S/D N+ implantation followed by a 20 sec RTA results in complete electrical activation of Arsenic dopants in the PolySi gate. Hence it does not result in Poly-Si gate depletion. Higher implant energy results in higher range and consequently reduced Poly-Si depletion width (Figure 4). It is observed that the tuning range improvement is a weak function of the low extension implant energy and low implant dose. Devices with lower extension implant energy (5KeV) show same improvement in tuning range indicating that, the proposed technique is insensitive to the process variations due to extension implantation. This will have implications in future technology node wherein the implant energy is reduced for the ultra shallow junction formation. This technique will still be useful in lower implant energy conditions. It is observed that, as RTA time increases the tuning range reduces (Figure 5). This can be attributed to the higher diffusion and electrical activation of the implants. With technology scaling and RTA time reducing; this technique will be more beneficial in incorporating the Poly-Si depletion effect effectively in the gate electrode thereby increasing the tuning range further. Figure 6 shows the effect of Poly-Si stack height on the tuning range. Tuning range increases with increase in the gate stack height due to increase in Poly-Si depletion width. As Poly-Si gate stack height is scaled down, the tuning range improvement is minimal as seen in 40nm stack height case. Thus Poly-Si stack height may limit the usefulness of this technique in future technologies. In conclusion, it is shown that tuning range in MOS varactors can be improved using poly-silicon depletion effect. It is achieved in the conventional CMOS process, without additional process complexity. It requires only the re-definition of masks related to deep source/drain and extension/halo implants. The improvement in tuning range strongly depends on the RTA time than the extension implant parameters. The effect of Poly-Si stack height on the tuning range is investigated. Similar tuning range improvement with the proposed technique is observed for N-well and P+ Poly-Si structure as shown in figure 7.