2006 64th Device Research Conference最新文献

{"title":"p-GaN/AlGaN/GaN Enhancement-Mode HEMTs","authors":"C. Suh, A. Chini, Y. Fu, C. Poblenz, J. Speck, U. Mishra","doi":"10.1109/DRC.2006.305167","DOIUrl":"https://doi.org/10.1109/DRC.2006.305167","url":null,"abstract":"GaN-based enhancement-mode (E-mode) HEMTs are attracting significant interest for integration of control circuitry and for the added safety of a normally-off device in power switching applications. While previous work reports excellent performance by gate-recessing' and Fluorine-based plasma treatment2, the Schottky gate turn-on voltage of these devices are at most 2 V. Because highpower switching applications require a threshold voltage of over 1 V for gate signal noise immunity, increasing the gate turn-on voltage is crucial. Utilization of p-GaN barrier below the gate3 depletes the channel and increases the gate turn-on voltage to 3 V, rendering it attractive for high-power applications. In this report we present a p-GaN/AlGaN/GaN E-mode HEMTs with a 3 V gate turn-on and maximum output current exceeding 0.3 A/mm. In addition, pulsed I-V measurement and small-signal performance of these devices are presented and the design space of p-GaN gated E-mode HEMTs are investigated for high-power switching applications.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114061715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"NMOS/SiGe Resonant Interband Tunneling Diode Static Random Access Memory","authors":"S. Sudirgo, D. Pawlik, S. Kurinec, P. Thompson, J. Daulton, S.-Y. Park, R. Yu, P. R. Berger, S. Rommel","doi":"10.1109/DRC.2006.305175","DOIUrl":"https://doi.org/10.1109/DRC.2006.305175","url":null,"abstract":"Tunneling-based static random access memory(SRAM)has been sought as a viable solution for a lowpower and high speed embedded memory application. The first cell design, proposed by Goto et al. [1],consists oftwotunnel diodes connected in series, oneacting as the drive andthe other as the load as showninFig. 1. This configuration allows for bistable operation at a particular range ofsupply voltages (VDD). Theinformation is stored at the sense node, whichcanbe altered by modulating current into the node via a FET.Byinjecting a current into the sense node, the cell is forced to latch to a high state as illustrated in Fig l(b).During write low operation, the FETis used to discharge the cell, pulling the sense node potential to a lowstate as depicted in Fig l(c). The demonstration ofthis type of bistable latch has been done in the Ill-Vmaterial system, showing avery promisingperformance bothin speedandpowerdissipation [2]. Morimotoetal. realizedthe systemin Si","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"74 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113997021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"FinFET Performance Enhancement with Tensile Metal Gates and Strained Silicon on Insulator (sSOI) Substrate","authors":"W. Xiong, K. Shin, C. Cleavelin, T. Schulz, K. Schruefer, I. Cayrefourcq, M. Kennard, C. Mazure, P. Patruno, T. Liu","doi":"10.1109/DRC.2006.305109","DOIUrl":"https://doi.org/10.1109/DRC.2006.305109","url":null,"abstract":"1. Texas Instruments Inc., SiTD, 13121 TI Boulevard, Dallas, TX USA 2. Dept. of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 3. Infineon Technologies, Am Campeon 1-12, 85579 Neubiberg, Germany 4. SOITEC S.A., Parc Technologique des Fontaines 38190 Bernin, France 5. Synopsys, Inc., 700 E. Middlefield Road, Mountain View, CA 94043 USA Phone: (510) 643-2639 Fax: (510) 643-2636, E-mail: ksshinweecs.berkeley.edu","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123911958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Depletion-Mode MOSFET on n-GaAs substrate with HfO2 and Silicon Interface Passivation","authors":"I. Ok, H. Kim, M. Zhang, T. Lee, F. Zhu, G. Thareja, L. Yu, S. Koveshnikov, W. Tsai, V. Tokranov, M. Yakimov, S. Oktyabrsky, Jack C. Lee","doi":"10.1109/DRC.2006.305112","DOIUrl":"https://doi.org/10.1109/DRC.2006.305112","url":null,"abstract":"High-k dielectrics, such as HfO2, have been considered as alternative to SiO2 in Si-based CMOS technology. The alternative dielectrics provide excellent opportunity for considering alternative channel materials such as GaAs. In this work, we present the electrical characteristics of TaN/HfO2/GaAs MOS capacitors with Si interface control layer (ICL) under various PDA (post-deposition anneal) condition and various Si deposition temperature/time and depletion mode MOSFET using optimum capacitance condition. Excellent electrical characteristics with thin EOT (-2nm), low frequency dispersion (<50/O) and high maximum mobility (568 cm2/V-s) have been obtained. Si ICL was deposited by sputtering of Si. PVD HfO2 films were deposited using the modulation technique [1], followed by PDA at 600°C in N2 (02 5%). Fig. 1 shows transmission electron microscopy (TEM) on the MOSCAP with 10nm HfO2 with PDA of 600°C 3 min. The interface between HfO2 and GaAs surface was degraded severely after 600°C 3 min PDA for sample without Si ICL. Electron energy loss spectroscopy (EELS) shows that Si was partially oxidized simply due to exposure to air after Hf deposition process (Fig. 2). In Fig. 3 and Fig. 4 TEM, EELS and energy dispersive X-ray spectroscopy (EDXS) show that after Imin Si ICL deposition, the interface Si changed to SiO2 with increasing PDA time or temperature while protecting GaAs surface. ICL thickness also changed. X-ray photoelectron spectroscopy (XPS) also show similar result in that with 1 min Si deposition time, Si was partially oxidized, and after Imin PDA in N2(O2 50 o), the Si ICL was oxidized to SiO2 (Fig. 5). However, if 2min Si ICL thickness was used, Si was not fully oxidized even after 15min PDA at 600°C (Fig. 6). Fig. 7 and Fig. 8 summarize the frequency dispersion characteristics (AV and 00 are defined in Fig. 7) versus Si ICL deposition condition as a function of PDA time for capacitor. With appropriate thickness of Si ICL, low frequency dispersion (< 50/O) can be obtained. In contrast, without Si ICL, frequency dispersion was around 25%. In general, Si deposition time of 60-100 second and longer PDA time resulted in reduced frequency dispersion. Frequency dispersion was more depended on Si deposition time than on PDA condition. The results suggest that there is negligible Fermi level pinning at the surface. Flat band voltage shift with different metal gate also provided good evidence for unpinned Fermi level (Fig. 9). Si deposition time of 60 second with 7min PDA time resulted in lower DA value using conductance method (Fig. 10). Fig. 11 demonstrates the linear dependence of the equivalent oxide thickness (EOT) on the physical thickness of HfO2. The k-value of the gate HfO2 was found to be k=19.5 (with ksIo2 = 3.9) [2]. Leakage current was reduced (to _10-5 A/cm2) by using the Si ICL for 4.Onm thick high-k dielectric in N-type GaAs wafer (Fig. 12). We have demonstrated depletion mode MOSFET using the optimum thickness and PDA condition (1 mi","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"616 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116338362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Demonstration of GaSb QW-based \"Buffer-Free\" LED on GaAs Substrate","authors":"M. Mehta, G. Balakrishnan, S. Huang, A. Khoshakhlagh, M. N. Kutty, L. Dawson, D. Huffaker","doi":"10.1109/DRC.2006.305155","DOIUrl":"https://doi.org/10.1109/DRC.2006.305155","url":null,"abstract":"The narrow band-gap III-Sb material system provides an excellent platform for development of infrared light emitters in the 1.55 to 5 ptm wavelength range. While high performance edge emitters have been demonstrated on GaSb substrates, similar success has not been seen with Sbbased Vertical-Cavity Surface-Emitting Lasers (VCSELs) due to the lack of a low-loss current and mode aperture that has been key to the success of As-based VCSELs. In this abstract we demonstrate a technology for development of Sb-based active regions on GaAs substrates using an interfacial misfit (IMF) dislocation array based nucleation, resulting in a \"buffer-free\" technology. The demonstrated device is an LED emitting vertically at 1.65 pIm with its DBRs grown directly on the GaAs substrate, without the use of any metamorphic buffers. The approach promises future devices such as VCSELs that may consist of arsenic based DBRs and Sb based active regions thus utilizing the long-wavelength Sb active regions while also incorporating the mature processing and manufacturing technology of GaAs. The scope of the technology is not restricted to GaAs substrates as has been shown by previously demonstrated results of optically pumped GaSb/Si VCSELs.1","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117057525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Charge Trapping WN Nano-dots with /or without Nitride Sub-layer for FinFET FLASH Memory","authors":"J. Choe, J. Lee, Y. Ahn, Se-Hoon Lee, B. Choi, Suk-kang Sung, E. Cho, S. Kim, S. Cheong, Choong-ho Lee, I. Chung, Kyuncharn Park, Donggun Park, B. Ryu","doi":"10.1109/DRC.2006.305179","DOIUrl":"https://doi.org/10.1109/DRC.2006.305179","url":null,"abstract":"Now flash memories using poly-Si floating gate are in front of their scaling limits. Nanocrystal or nano-dot trapping memory is a candidate for one of future scaled flash memories. Many efforts with semiconductor nanocrystals such as Si or Ge have just a small memory window [1-5]. Some other experiments using metal nanocrystal have been made to improve threshold voltage shift, but their endurance and retention characteristics are not satisfied. In this work, we will report the discrete charge trapping WN nano-dots for FinFET flash memory. We also investigate whether an additional thin nitride sub-layer is useful or not. In the fabrication of body-tied FinFET Flash memory using WN nano-dots, 3.5 nm-thick SiO2 films containing nitrogen were grown by dry oxidation after the active fin formation and shallow trench isolation processes. Fin structured MOSFET has an advantage to increase the number of nano-dots per cell due to the enlarged active area. In addition, FinFET structure is expected to provide the better program inhibition characteristics owing to the superior punch-through controllability of the transistor. For the trap layer, the WN nano-dots were deposited using a pulsed nucleation layer CVD method with B2H6, WF6, and NH3 gases. WN nano-dot process is optimized through controlling gas flow rate, process temperature, and cycle numbers in the kinetically limited process regime. A cross-sectional TEM and SEM micrograph ofWN nano-dot device with very thin SiN layer with 2 nm thickness are shown in Fig.1 (a) and (b). Si fin height is almost 100 nm and gate length is 55 nm. It is clearly observed that the WN nano-dots are embedded between the thin nitride layer and control oxide(A1203 with 12.2 nm thickness). The mean size of dots and aerial density are estimated to be about 3 5 nm and lx 1012cm2, respectively. The work-function ofWN turns out to be 4.65 eV by the method in [6], and it is expected to provide 1.2 eV deeper trap sites than average trap level of SiN layer considering energy band diagram as shown in Fig. 2. For the blocking dielectrics, amorphous AlxOy layer deposited by ALD CVD process followed by post-anneal at 950°C, 30 sec to make it a crystalline phase of A1203. A1203 layer as a blocking oxide demonstrate more than 4 orders of magnitude smaller leakage current properties on annealing temperature. From EDX spectrum analysis, it is found that there is no W diffusion into the tunnel oxide after 1000°C anneal treatment. After 16V, 100[ts program stress, threshold voltage shift is measured over 4.2 V from ID-VG characteristics as shown in Fig. 3. Program and erase stresses with 16V, 100[ts and -16V, lOOms induced flat band voltage shifts, respectively. Fig. 4 exhibits the capacitance-voltage characteristics of initial, program, and erase state (a)with and (b)without thin nitride under-layer. In case of (a) with thin SiN under-layer, the AVFB is 3.84V and it is larger than that of case (b). We think that bulk traps in SiN sub-layer a","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125568097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Elemental devices for monolithic optoelectronic integrated circuits on lattice-matched Si/III-V-N/Si structure","authors":"Y. Furukawa, H. Yonezu, A. Wakahara, Y. Morisaki, S. Moon, S. Ishiji, M. Ohtani","doi":"10.1109/DRC.2006.305103","DOIUrl":"https://doi.org/10.1109/DRC.2006.305103","url":null,"abstract":"Optoelectronic integrated circuits (OEICs) have been expected for realization of novel devices and circuits. It is necessary for realization of OEICs to combine Ill-V compounds and Si with high quality. However, many dislocations were induced by the large difference in valence electron and lattice-constant between Ill-V compounds, such as GaAs and InP, and Si. We have already realized a dislocation-free and lattice-matched Si/GaPN/Si using molecular beam epitaxy (MBE)[1]. In addition, a dislocation-free InGaPN/GaPN double hetero (DH) light emitting diode (LED) has been realized on a Si substrate[2]. If these technologies are merged systematically, the top Si layer and III-V-N alloys will be used for integrated circuits and optical devices, respectively, as shown in Fig. 1 [3]. In this study, we have investigated a fabrication process for monolithic OEICs based on Si/III-V-N/Si structure and realized MOSFETs and LEDs in the same Si/III-V-N/Si wafer. A Si/III-V-N/Si wafer was grown by MBE, as shown in Fig. 2. A p-Si(100) substrate misoriented 40 toward [011] direction with carrier concentration of 5x1 OI8cm3 was used as a substrate. A GaP layer grown by migration enhanced epitaxy (MEE) is necessary to solve the difference in valence electron between Si and Ill-V compound semiconductors. An InyGa1-yPO.96No.04/GaPo.98No.o2 DH structure was grown at 500°C in the III-V-growth chamber. The GaP098N002 layers are lattice matched to Si. InyGa1 yP0.96No.04 layer is an active layer for DH LEDs. After the growth of DH structure, a thermal treatment was performed at 450°C and the sample was transferred to the Si-growth chamber through a vacuum chamber. A 1 ptm-thick Si layer was grown by electron-beam evaporator on the n-GaPN layer. A carrier concentration in the Si epilayer of 4x1017cm-3 was measured by four-point probe method. A fabrication sequence is proposed in Fig. 3. A 1ptm-thick field-oxide layer was deposited by chemical vapor phase deposition after separating LED regions by reactive ion etching. For simplicity of the process, a thermal annealing to increase the luminescence efficiency and a post-annealing of ion-implantation were combined with a gate-oxidation process. The luminescence of GaPN layers has been increased by the annealing at 900°C for 1-10min[4]. Thus, gate-oxidation was performed at 900°C for 10min in a wet 02 ambient, since a growth rate is higher than that in dry oxidation. Figure 4 shows a micrograph of a chip fabricated through the OEIC process. pMOSFETs and LEDs are shown in the same chip. Capacitance-voltage characteristics of MOS diodes showed surface inversion. The thickness of gate oxide was estimated at 16nm, which was close to a thickness of oxide grown on a bare n-Si wafer as a reference. The carrier concentration was estimated at 6.6x1 017cm-3. The wet oxidation was found to be utilized for the OEIC process. Figure 5(a) shows typical characteristics of drain currents(IdS) versus drain voltages(Vd,). Although a threshold vo","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125828117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Very Low-Threshold 1.55-μm Dilute-Nitride Lasers","authors":"S. Bank, H. Bae, L. Goddard, H. Yuen, M. Wistey, J. Harris","doi":"10.1109/DRC.2006.305102","DOIUrl":"https://doi.org/10.1109/DRC.2006.305102","url":null,"abstract":"The initial discovery of anomalous bowing in GaInNAs by Kondow and coworkers [1] has prompted great interest in developing high-performance GaAs-based lasers in the 1.2-1.6 pm range to replace InP-based sources. Nitrogen reduces the bandgap almost exclusively in the conduction band, naturally reducing the effects of carrier leakage and increasing the laser stability with ambient temperature. Moreover, the GaAs-based device structure can leverage the GaAs/AlAs material system for distributed mirrors in vertical-cavity surface-emitting lasers (VCSELs). Great strides in growth techniques have produced low-threshold edge-emitting lasers 300 A/cm2 and VCSELs at 1 .3-pm [2], [3]. However, device performance has lagged substantially in the 1.55-pm region (see Fig. 1) due to the growth difficulties associated with the high indium and nitrogen contents required. We present substantially improved 1.55-pm edgeemitting lasers with thresholds comparable to their 1.3-pm counterparts and competitive to their InP-based devices.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125874932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-Performance Enhancement-mode ZnO Nanowire Field-Effect Transistors with Organic Nanodielectrics: Effects of Ozone Treatments","authors":"Sanghyun Ju, Kangho Lee, Myung‐Han Yoon, A. Facchetti, T. Marks, D. Janes","doi":"10.1109/DRC.2006.305079","DOIUrl":"https://doi.org/10.1109/DRC.2006.305079","url":null,"abstract":"Nanowire transistors are of significant interest for future electronic and optoelectronic applications, including flexible electronics and displays. While relatively high mobilities have been achieved in nanowire transistors using various semiconductors, the transistors reported to date typically suffer from relatively poor on/off ratios, due to the relatively thick gate dielectrics and the use of metal (Schottky) source/drain contacts to moderate band-gap materials, which leads to ambipolar effects. ZnO nanowire field-effect transistors (ZnO NW-FETs) are of particular interest for future display devices because of the potential transparency due to the wide bandgap (3.37 eV), as well as the inherent flexibility of nanowires. Initial studies of ZnO NW-FETs showed mobilities significantly lower than bulk values.' As fabricated, the ZnO-NW FETs in our prior work exhibited good transistor characteristics, although the measured subthreshold slopes and on/off ratios were not suitable for large-scale integration.2 In this study, we report significant improvements in device performance metrics following annealing and ozone treatment ofZnO NW-FETs. The single-wire device structure (Fig. 1) uses a heavily doped ntype Si substrate as a common back-gate and aluminum (Al) source/drain contacts. The crystalline nanowires had a diameter of approximately 120 nm. The gate dielectric consists of three layer-by-layer self-assembled organic trilayers (15 nm).3 This self-assembled superlattice (SAS) film is compatible with lithographic processes, and exhibits excellent insulating properties (Fig. 2) with a large specific capacitance (180 nF/cm2) and a low leakage current density (1 X10-6 A/cm2 up to 2V). The device characteristics following annealing and ozone treatments are illustrated for a representative device in Figs. 3 (a) and 3 (b). First, annealing in air (130°C, 15 min) was performed to reduce fixed positive charges in the SAS,3 resulting in an improved subthreshold slope (230 mV/dec). The on-current degraded upon 4 annealing, consistent with reported annealing-induced effects on ZnO nanowires. Compared to asfabricated devices, subsequent ozone treatments resulted in complete on-current recovery, a positive threshold voltage (Vth) shift from -0.4 V to 0.2 V, a subthreshold slope reduction from 400 mV/dec to 130 mV/dec and a large on-off current ratio (-10o7). The resulting enhancement-mode devices operate at subIV with an on-current of 4 ,uA at 0.9V and a transconductance of 1.4 ,uS (Fig. 3). The effective mobility, extracted from the measured transconductance and a cylindrical capacitance model, is as high as -1200 cm2/V-sec. Since I-V based mobility extraction does not permit independent determination of carrier concentration and mobility, an extended analysis is being developed to explain the relatively large value compared to bulk ZnO mobility ( 200 cm2/V-sec). Nominally undoped ZnO nanowires are lightly doped n-type, so Al is expected to have a good wor","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122830499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Germanium Passivation for High-k Dielectric III-V MOSFETs and Temperature Dependence of Dielectric Leakage Current","authors":"H. Kim, I. Ok, M. Zhang, T. Lee, F. Zhu, G. Thareja, L. Yu, S. Koveshnikov, W. Tsai, V. Tokranov, M. Yakimov, S. Oktyabrsky, Jack C. Lee","doi":"10.1109/DRC.2006.305131","DOIUrl":"https://doi.org/10.1109/DRC.2006.305131","url":null,"abstract":"We present depletion mode MOSFETs on the MBE grown n-GaAs layer with germanium (Ge) passivation layer, high-k HfO2 dielectric, and TaN metal gate showing excellent transistor characteristics (pleff376 cm2/Vs, gm 68 mS/mm) and ultra-thin EOT of 17 A. We also investigate the temperature dependence (ranging from 25°C and 125°C) of leakage currents in various gate dielectric stacks deposited on GaAs such as HfO2, HfO2/Si/Ge, and HfO2/Ge using the MOSCAPs with EOT ranging from 30 A to 11 A. The most challenging issue in GaAs devices is the lack of stable nature gate oxide such as SiO2 on Si substrate [1-3]. We used Ge single layer or silicon (Si)/Ge double layer as interfacial control layer (ICL) to passivate GaAs surface. From HfO2 MOSCAPs on n-GaAs(100) substrate, we obtained remarkable results such as small C-V frequency dispersion (< 8 %) and EOT of 11 A (HfO2 70 A) with low dielectric leakage current of _10-6 A/cm2 at VG-VFB = 1 V by employing Ge ICL [4]. Due to an additional introduction of Si layer, MOSCAPs with Si/Ge ICL show relatively thicker EOT (4-5 A) and reduced dielectric leakage current compared to the device with Ge only ICL (Fig. 1 and 2) at a given thickness of HfO2. As also shown in Fig. 1 and 2, without any passivation layer, HfO2 MOSCAPs show much thicker EOT and larger dielectric leakage current. These results indicate that Ge or Si/Ge ICL passivate effectively the GaAs surface sustaining high quality interface (Dit1011 1012/cm2-eV from Terman method). Fig. 3 shows the dielectric leakage currents as a function of operating temperature varying from 25°C to 125°C in the MOSCAPs with HfO2, HfO2/Si/Ge, and HfO2/Ge gate dielectric stacks. It is obvious that increase in dielectric leakage current according to temperature is much larger in the devices with only HfO2 gate dielectric stack in comparison with the devices with Ge and Si/Ge ICL. This indicates that Poole-Frenkel conduction becomes dominant and interface quality is not good as the devices with Ge or Si/Ge ICL, for which tunneling mechanism dominates. Fig. 4 shows schematic GaAs MOSFET structure and ring-type MOSFET structure. 600 A-thick","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129929530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}