Charge Trapping WN Nano-dots with /or without Nitride Sub-layer for FinFET FLASH Memory

Abstract

Now flash memories using poly-Si floating gate are in front of their scaling limits. Nanocrystal or nano-dot trapping memory is a candidate for one of future scaled flash memories. Many efforts with semiconductor nanocrystals such as Si or Ge have just a small memory window [1-5]. Some other experiments using metal nanocrystal have been made to improve threshold voltage shift, but their endurance and retention characteristics are not satisfied. In this work, we will report the discrete charge trapping WN nano-dots for FinFET flash memory. We also investigate whether an additional thin nitride sub-layer is useful or not. In the fabrication of body-tied FinFET Flash memory using WN nano-dots, 3.5 nm-thick SiO2 films containing nitrogen were grown by dry oxidation after the active fin formation and shallow trench isolation processes. Fin structured MOSFET has an advantage to increase the number of nano-dots per cell due to the enlarged active area. In addition, FinFET structure is expected to provide the better program inhibition characteristics owing to the superior punch-through controllability of the transistor. For the trap layer, the WN nano-dots were deposited using a pulsed nucleation layer CVD method with B2H6, WF6, and NH3 gases. WN nano-dot process is optimized through controlling gas flow rate, process temperature, and cycle numbers in the kinetically limited process regime. A cross-sectional TEM and SEM micrograph ofWN nano-dot device with very thin SiN layer with 2 nm thickness are shown in Fig.1 (a) and (b). Si fin height is almost 100 nm and gate length is 55 nm. It is clearly observed that the WN nano-dots are embedded between the thin nitride layer and control oxide(A1203 with 12.2 nm thickness). The mean size of dots and aerial density are estimated to be about 3 5 nm and lx 1012cm2, respectively. The work-function ofWN turns out to be 4.65 eV by the method in [6], and it is expected to provide 1.2 eV deeper trap sites than average trap level of SiN layer considering energy band diagram as shown in Fig. 2. For the blocking dielectrics, amorphous AlxOy layer deposited by ALD CVD process followed by post-anneal at 950°C, 30 sec to make it a crystalline phase of A1203. A1203 layer as a blocking oxide demonstrate more than 4 orders of magnitude smaller leakage current properties on annealing temperature. From EDX spectrum analysis, it is found that there is no W diffusion into the tunnel oxide after 1000°C anneal treatment. After 16V, 100[ts program stress, threshold voltage shift is measured over 4.2 V from ID-VG characteristics as shown in Fig. 3. Program and erase stresses with 16V, 100[ts and -16V, lOOms induced flat band voltage shifts, respectively. Fig. 4 exhibits the capacitance-voltage characteristics of initial, program, and erase state (a)with and (b)without thin nitride under-layer. In case of (a) with thin SiN under-layer, the AVFB is 3.84V and it is larger than that of case (b). We think that bulk traps in SiN sub-layer and WN nano-dot/SiN interface traps assist larger memory window. In addition, thin SiN layer is considered as a diffusion barrier ofW or WN atoms so that there is no degradation of tunneling oxide. Fig. 5 represents the retention characteristics ofWN nanodot FinFET (a)with and (b)without thin nitride layer. It is cleared confirmed that WN nano-dot memory cell with thin nitride sublayer has a good retention characteristics up to 105 sec at room temperature. It is considered that there are tunnel oxide degradations due to local W atom diffusion into thin oxide layer ifwe do not use SiN barrier layer. Concerning the concept of dot surface and defect level engineering, WN dot surface is so highly curved that the surface is more strained in comparison with the plane surface, which causes high defect density around each of WN nano-dots. In addition to that, WN dot has so high permittivity like a conducting sphere that the local electric field near channel area increase, which enhances the Fowler-Nordheim (F-N) tunneling probability. Consequently these are attributed to the thinning tunneling oxide and the large capturing efficiency of WN dots in case tunneling oxide degradations due to W diffusion are effectively protected. We have demonstrated the WN nano-dot/thin SiN stacked FinFET characteristics for NVM device application. WN nano-dots with thin SiN sub-layer are certainly applicable as a charge storage node.