2006 64th Device Research Conference最新文献

{"title":"Low-Voltage, Low-Power Organic Complementary Circuits with Self-Assembled Monolayer Gate Dielectric","authors":"H. Klauk, U. Zschieschang","doi":"10.1109/DRC.2006.305062","DOIUrl":"https://doi.org/10.1109/DRC.2006.305062","url":null,"abstract":"Organic transistors often require minimum operating voltages of 10 V or more, since they typically use inorganic or polymeric gate insulators with a relatively small dielectric capacitance (<1 0-7 F/cm2). Lower operating voltages are desirable for certain applications, either to relax power supply requirements, to extend battery life, or to make large-area organic electronics compatible with silicon-CMOS peripheral circuitry. Recently, p-channel organic TFTs with molecular self-assembled monolayer [1] or multilayer [2] gate dielectrics have been demonstrated. With a gate dielectric capacitance approaching 10-6 F/cm2 these transistors can be operated with voltages of just a few volts. Low-voltage digital circuits with p-channel enhancement-mode loads have also been demonstrated [3]. To realize the full potential of ultra-thin gate dielectrics for truly low-power digital and analog organic circuits, we report here on the first n-channel TFTs and the first organic complementary circuits with monolayer gate dielectrics.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116053582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Widely tunable single-chip transceiver for 10 Gb/s wavelength conversion","authors":"M. Dummer, M. Sysak, J. Raring, A. Tauke-Pedretti, L. Coldren","doi":"10.1109/DRC.2006.305098","DOIUrl":"https://doi.org/10.1109/DRC.2006.305098","url":null,"abstract":"Wavelength conversion is an essential function in wavelength-division-multiplexing (WDM) optical networks, as it enables better utilization of bandwidth and reduces blocking probabilities. This work presents, for the first time, a fully integrated transceiver solution to wavelength conversion in which all microwave signals are confined on a single InP chip. This device architecture, referred to as a photocurrent-driven wavelength converter (PD-WC), is particularly attractive due to the potential for low power dissipation, high bandwidth, data regeneration, and no optical output filtering requirement unlike many all-optical implementations. Here, a termination resistor and DC-blocking capacitor are integrated with an electroabsorption modulator (EAM) based PD-WC such that only DC biases are necessary for device operation and no microwave signal must travel off the chip. This widely-tunable device demonstrates error free 10 Gb/s conversion and utilizes both a simple, single-regrowth fabrication and a simple bias configuration.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115385773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Iodine-doped pentacene schottky diodes for high-frequency RFID rectification","authors":"Daniel C. Huang, V. Subramanian","doi":"10.1109/DRC.2006.305065","DOIUrl":"https://doi.org/10.1109/DRC.2006.305065","url":null,"abstract":"In recent years, there has been substantial interest in the development of printed RFID tags, primarily driven by the expectation of a substantial lowering in cost. Based on current standards, the most promising frequency for low-cost RFID is 13.56MHz. For low-cost RFID applications, the tags will be passive; i.e., these tags will operate on power supplied inductively by the reader. While the logic circuitry on the tag will operate only at approximately 200kHz, the rectification circuitry required to convert the harvested AC signal to DC will necessarily operate at 13.56Mhz. The antenna section in a 13.56MHz tag consists of an inductor+capacitor tank tuned to the frequency of operation. The signal is then rectified and filtered, producing a DC signal to power the RFID circuit. A high performance diode is one of the most likely candidates for this rectification. We have already demonstrated high quality printed capacitors and inductors [1]. Most recently, several groups have reported organic diode operation at 13.56MHz. However, to achieve this high frequency operation, the groups have used incident AC signals of >30V, which are only possible for extremely short range tag operation; to achieve operation in the 10cm range, it will be necessary to realize high frequency diodes capable of efficiently extracting power at 13.56MHz at lower incident voltages.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"26 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126050700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Single-electron devices with granulated film cotunneling suppressors","authors":"A. Orlov, Xiangning Luo, T. Kosel, G. Snider","doi":"10.1109/DRC.2006.305081","DOIUrl":"https://doi.org/10.1109/DRC.2006.305081","url":null,"abstract":"Single-electron devices where a well-determined number of electrons can be controllably transferred continue to attract significant attention as one of the promising devices for applications in future digital circuits and metrology. However, the family of devices based upon precise transfer of single electrons (single-electron pumps, turnstiles, traps, latches and Quantumdot Cellular Automata (QCA) ) suffers from errors caused by cotunneling [1]. Cotunneling, a macroscopic quantum process, impairs the operation of devices where charge transfer is actuated by controllable Coulomb barriers, because it opens a classically prohibited channel for charge transfer under that barrier. A traditional way to reduce the cotunneling [2] is to increase the number of tunnel junctions in the device, N, because cotunneling current scales as I V 2N-1. For small biases the cotunneling current is thus significantly reduced. In practice, this approach has a significant drawback due to the inevitable presence of random background charges on the islands of the array. The need to individually adjust the random offset charges drastically complicates the operation and tuning of the devices. Here we present a different approach to suppress the cotunneling using a granulated metal film (Cr evaporated in 02 ambient) (Fig. 1) with weakly insulating properties. First, we fabricated and tested a single-electron transistor (SET) where suppression of the cotunneling is achieved by replacing the traditional metal island with a granulated metal film (Fig. 2). The SET has a characteristic charging energy defined by the welldefined Al/AlOx junctions while strongly suppressing the cotunneling by electron scattering in the granulated metal island (Fig 3). The value of the charging energy of the SET, EcSET z 0.27 meV exceeds the activation energy within the film, AE, by more than one order of magnitude. Therefore, with respect to the external gate, the granulated metal island can be viewed as a \"good\" metal and CBOs are completely defined by the larger scale parameter, EcSET >> AE. Second, using this design, we fabricated and tested a single-electron latch which utilizes this technology to achieve cotunneling suppression. A single-electron latch [3] consists of three dots connected in series by tunnel junctions. To achieve memory function in a latch the cotunneling must be suppressed. In previous demonstrations of single electron latches lithographically defined multiple tunnel junctions (MTJ) were used to connect the dots in a latch. The use of MTJs, however, requires complicated cancellation of the background charges affecting parasitic islands of the MTJs. In this work we use a granulated metal oxide film as the material for the middle dot (Fig. 4) that also acts as a cotunneling suppressor, replacing lithographically defined MTJs. The granulated metal film acts as a network of tunnel junctions and thus hampers the cotunneling while the presence of random offset charges localized in ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129445640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimal Spacing of Carbon Nanotubes in a CNFET Array for Highest Circuit Performance","authors":"A. Raychowdhury, A. Keshavarzi, J. Kurtin, V. De, K. Roy","doi":"10.1109/DRC.2006.305152","DOIUrl":"https://doi.org/10.1109/DRC.2006.305152","url":null,"abstract":"Carbon Nanotube field effect transistors (CNFETs) have appeared as very promising alternatives to traditional Si MOSFETs. It has often been argued, mostly qualitatively, that single CNT transistors would not be useful for VLSI, and one needs to have transistor arrays to get sufficient current out of them particularly to drive fixed capacitive loads. In this paper we investigate the optimal spacing of carbon nanotubes in an array for the highest performance. The CNFET that we have used in our analyses are Schottky Barrier CNFETs (Fig. la) with mid-gap Source/Drain work function, 20nm ballistic channel, a planar top gate with a 2nm thick HfO2 dielectric. It works on the principle of barrier thickness modulation by a gate voltage and carrier tunneling through the Schottky barrier (Fig. lb). The simulation methodology for CNFETs using NEGF as described in [2] has been used in this paper. To estimate the coupling between nanotubes, Poisson Equation is solved in 3D for arrays of CNTs. End effects have been neglected. The numerical I-V and C-V data have been imported to a circuit simulator and solved. Fig. 2a illustrates the top gate structure and Fig. 2b illustrates how the charge is distributed on the gate, for different T0x For high performance it is imperative to use well controlled growth processes where one would be able to synthesize an array of parallel carbon nanotubes with proper source/drain and gate structures. Let us consider a width of 100nm where CNTs of diameter d and inter-nanotube spacing, S need to be laid out in the form of an array (Fig. 3a). Let us consider that this transistor is driving an identical transistor. From a device design perspective, the optimal spacing S has been proposed to be approximately two times the CNT diameter (S=2d) [3] or S=2d + 4T0,. [4]. However, a circuit level analysis should also incorporate the role of parasitic and load capacitances. The parasitics (like the gate overlap or contact) scale with the transistor width, whereas pin and interconnect capacitances do not. We have two cases to consider: 1. Intrinsic load case: On one hand we can only have the intrinsic load capacitance corresponding to a CNFET driving another CNFET. This includes the device capacitance and is proportional to the number of tubes N. The delay of such a transistor can be simplified to: Low(CEXT PER TUBE X No. of Tubes)VDD (CPER TUBE )DD LwLOAD TPEP x No.ofTubes I (1) ION IPER TUBE X No. of Tubes IPER TUBE","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129495085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Large-area Electronics Based on Organic Transistors","authors":"T. Someya, T. Sakurai, T. Sekitani","doi":"10.1109/DRC.2006.305060","DOIUrl":"https://doi.org/10.1109/DRC.2006.305060","url":null,"abstract":"We report technical details of large-area sensors and actuators using organic field-effect transistors (FETs). In particular, we focus on stretchable electronic artificial skins (e-skins) for robots in the next generations and sheet-type Braille display with soft actuator arrays. We also present recent progress of reliability and stability issues; encapsulation techniques to suppress chemical degradation and annealing techniques to reduce the effect of DC bias stress. Furthermore, we report inkjet and screen printing process to manufacture 30X30 cm2 organic FET active matrices for applications to large-are sensors.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128554238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance of spin-based current-gating devices","authors":"M. Flatté, K. Hall","doi":"10.1109/DRC.2006.305073","DOIUrl":"https://doi.org/10.1109/DRC.2006.305073","url":null,"abstract":"Michael E. Flatte* and Kimberley C. Hall** *Department of Physics and Astronomy, University of Iowa, Iowa City, IA 52242 USA Phone:+1-319-335-0201, Fax:+1-319-353-1115, Email: michael_flatte(mailaps.org **Department of Physics, Dalhousie University, Halifax, Nova Scotia B3H 4R2 Canada Phone:+1 -902-494-7109, Fax:+1 -902-494-5191, Email: Kimberley.Hall(dal.ca We have compared the fundamental limits of performance of an individual spin-based current-switching device with an individual charge-based current-switching device. All the contacts to each of the devices are assumed to be incoherent\"; no quantum mechanical phase relation is maintained by electrons in the contact regions. We find that the use of spin-encoded information within the spin-based current-switching device leads to dramatic improvements in dynamic and static power dissipation relative to charge-based devices, and bypasses current roadblocks to charge device scaling. This includes a lower threshold voltage and lower capacitance than on the semiconductor roadmap for field effect transistors for logic through 2018. The charge-based current switching numbers for comparison have been taken from the semiconductor roadmap[l], which provides targets for complementary metal oxide semiconductor (CMOS) field-effect transistors (FETs) over the next 15 years. As the interest here is on low power dissipation, the focus of the comparison will be on the low standby power (LSTP) branch of the roadmap. The elements of transistor power dissipation examined include the leakage current and gate switching energies, gate switching speed, sourcedrain saturation current, and gate capacitance. In this analysis any benefit of coupled spin-based transistors is neglected (e.g. the design of a spin-based circuit to act as an XOR gate). A controllable spin lifetime forms the basis for transistor action in the device we consider[2]. Once polarized spins (to be specific, spin-up) have been injected into a channel, either from a magnetic material or using a nonmagnetic spin filter, their motion through the device can be controlled according to whether they remain spin polarized or not. If they remain spin polarized, and the drain contact spin filter only accepts spin-down carriers, then current does not flow from source to drain. This is the situation when no electric field is applied using the gate contact. When an electric field is applied then the spin polarization decays rapidly in the channel. In this situation current flows easily from source to drain. So in this design there is no moveable barrier between source and drain. The spin-dependent barriers in this device permit carriers of one spin orientation to pass while preventing those of the other spin polarization. These barriers are not raised or lowered. The source-drain current is proportional to the spin relaxation rate, so for a 10 ps spin lifetime in the \"on\" state and a 105 on-off ratio the spin lifetime must be 1 Fis in the off state (100 Fis for a ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125643093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Seamless transition from the single-electron regime to field-effect transistor operation of nanoscale Schottky-barrier FETs","authors":"K. Indlekofer, J. Knoch, J. Appenzeller","doi":"10.1109/DRC.2006.305080","DOIUrl":"https://doi.org/10.1109/DRC.2006.305080","url":null,"abstract":"One of the major challenges for the simulation of nanoscale field-effect transistors (FET) consists in an adequate description of the Coulomb interaction within the transistor channel: a proper simulation approach has to account for the Coulomb interaction of a few fluctuating electrons and at the same time has to be able to describe non-equilibrium transport in an open nanosystem. Present device simulators, however, only deal with one of the two aspects: For instance, in the limit of a quasi-isolated quantum dot system, the orthodox theory of many-body Coulomb interaction [1] correctly describes single-electron charging effects such as Coulomb blockade [2,3] but does not account for renormalization and dissipation tefms which are important in open transistor systems. On the other hand, the non-equilibrium Green's function formalism (NEGF) [4] is the most appropriate approach for the simulation of quantum transport in realistic device systems. However, a Hartree approximation is commonly employed (selfconsistent potential), rendering the approach unable to describe the Coulomb interaction of a few fluctuating electrons. Recently, we have presented a novel multi-configurational selfconsistent Green's function approach (MCSCG) [5] which allows for the inclusion of few-electron Coulomb interaction effects within the framework of the NEGF. In this paper, we present for the first time a direct comparison of a conventional Hartree NEGF calculation with the results of the MCSCG approach. It will shown that the MCSCG is able to describe Coulomb blockade effects in the low temperature limit, while for the case of strong nonequilibrium and room temperature conditions, the Hartree approximation is retained. Hence, the MCSCG approach covers the single-electron transport regime as well as the transistor operation at room temperature. Deviations from a mean-field approximation become most apparent in a system with quasi-bound states, exhibiting single-electron charging effects as a function of external electrode potentials. As a typical example, we will therefore consider a one-dimensional (ID) coaxially gated nanowire transistor with Schottky-barrier source and drain contacts [5] as sketched in Fig. 1. Here, we assume a channel length of L = 20nm with a diameter of dnt = 4nm, surrounded by a gate oxide with do, = 10nm. For such a system, the Coulomb interaction within the channel becomes equivalent to an effective 1D interaction [6]. As a key element, our algorithm identifies trapped single-electron states which are subject to occupation fluctuations. To a good approximation, the system Green's functions can then be written as a weighted average over many-body configurations, which are defined as eigenstates of a projected many-body Hamiltonian within the Fock-subspace of quasi-trapped single-particle states. Fig.2 visualizes the simulated drain current ID for the single-electron transport regime (T= 77K) as a grayscale plot. In contrast to the Hartree-only c","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127412536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Super-self-aligned back-gate/double-gate planar transistors with thick source/drain and thin silicon channel","authors":"Hao Lin, H. Liu, A. Kumar, U. Avci, J. VanDelden, S. Tiwari","doi":"10.1109/DRC.2006.305108","DOIUrl":"https://doi.org/10.1109/DRC.2006.305108","url":null,"abstract":"This work presents a reproducible super-self-aligned approach to the fabrication of back-gate/double-gate transistors with thin silicon channels and thick source/drain poly-silicon access regions. Both n-channel and p-channel devices exhibit high drive currents, strong back-gate control and high effective carrier mobility. The unique attributes of our approach include a very effective control of 1) the silicon channel thickness, 2) thick source/drain formation, 3) solidstate diffused junctions from the doped poly-silicon source/drain into the un-doped Si channel, and 4) super-self-alignment between the back gate and the front gate with additional buried interconnections among devices. This approach eliminates the need of epitaxial growth of silicon and irreproducibility of wet etching to form back gate under cut of previous studies.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128076344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 154-GHz Static Divider in 0.25 μm InP DHBT Technology","authors":"N. Phan, D. Sawdai, B. Oyama, P. Chang, D. Scott, A. Gutierrez-Aitken, A. Oki","doi":"10.1109/DRC.2006.305058","DOIUrl":"https://doi.org/10.1109/DRC.2006.305058","url":null,"abstract":"Static dividers are well recognized performance benchmarks for mixed-signal technologies. We report an emitter-coupled logic (ECL) static divider with a maximum operating frequency of 154.75 GHz. The same divider was demonstrated to operate down at 5 GHz at the same bias, dissipating 222.11 mW. The circuit was fabricated in a high performance 0.25-pm InP DHBT technology withfT> 300 GHz andfmax > 450 GHz. We discuss device, processing, and circuit design. The InP/InGaAs/InP double HBTs were grown by solid source molecular beam epitaxy. The HBT layer structure includes an InP emitter, a 300-A compositionally graded InGaAs base doped with beryllium at 8x1019cmM3, and a 1200-A InP collector. After HBT fabrication, the devices were planarized with a spin-on dielectric, and vias were etched down for the emitter, base, and collector contacts. The backend process included thin-film resistors, metal-insulator-metal capacitors, 4 levels of planarized interconnect on low-K dielectric, and optional back-side thinning / vias / metallization. Figure 1 shows the cross-section of a finished HBT with a 0.25-ptm emitter and a segment of a circuit with 4 levels of interconnect. HBTs were fabricated with emitter widths as small as 0.14 ptm; however, scaling effects related to the base contact width caused the 0.25-ptm HBTs to give the best high-frequency performance. Typical current gain (P) is between 20 and 30, and the breakdown voltage (BVCEO) is 4 V. The HBT is designed for peak RF performance at a moderately high JE = 7 mA/ tm2 (see Figure 2). Peak fT 322 GHz occurs at VCB 0.27 V when the collector is partially undepleted for reduced transit time, and peakfmax 459 GHz occurs at VCB 0.78 V when the collector is fully depleted and CBC is minimized. Figure 3 illustrates the major blocks of our static divider. Static divider design in the D-Band regime poses many challenges. First, transistors operating at such high frequencies in ECL topologies are prone to oscillation. Next, the time constants at the latch load nodes can limit high-speed performance. Capacitances from conventional, transistor current sources begin to become limiting time constants as well. The interface circuitry to and from the actual divider core must be carefully designed to not mask core performance. Input reflections and circuit bandwidth make it challenging for the input path to provide adequate power and slew rate to switch the core. Today, D-Band sources are single-ended, where headroom can also limit the maximum signal level delivered to the core. The divider core output must contend with the parasitic capacitance of the feedback path as well as the loading of subsequent output stages. Employing high bandwidth circuit techniques can sometimes be detrimental to low frequency performance, further exacerbating the challenge of static divider design. Finally, power must be considered for practical systems. Each of the mentioned challenges was addressed in the divider design. The divider was ","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128485482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}