A 154-GHz Static Divider in 0.25 μm InP DHBT Technology

Static dividers are well recognized performance benchmarks for mixed-signal technologies. We report an emitter-coupled logic (ECL) static divider with a maximum operating frequency of 154.75 GHz. The same divider was demonstrated to operate down at 5 GHz at the same bias, dissipating 222.11 mW. The circuit was fabricated in a high performance 0.25-pm InP DHBT technology withfT> 300 GHz andfmax > 450 GHz. We discuss device, processing, and circuit design. The InP/InGaAs/InP double HBTs were grown by solid source molecular beam epitaxy. The HBT layer structure includes an InP emitter, a 300-A compositionally graded InGaAs base doped with beryllium at 8x1019cmM3, and a 1200-A InP collector. After HBT fabrication, the devices were planarized with a spin-on dielectric, and vias were etched down for the emitter, base, and collector contacts. The backend process included thin-film resistors, metal-insulator-metal capacitors, 4 levels of planarized interconnect on low-K dielectric, and optional back-side thinning / vias / metallization. Figure 1 shows the cross-section of a finished HBT with a 0.25-ptm emitter and a segment of a circuit with 4 levels of interconnect. HBTs were fabricated with emitter widths as small as 0.14 ptm; however, scaling effects related to the base contact width caused the 0.25-ptm HBTs to give the best high-frequency performance. Typical current gain (P) is between 20 and 30, and the breakdown voltage (BVCEO) is 4 V. The HBT is designed for peak RF performance at a moderately high JE = 7 mA/ tm2 (see Figure 2). Peak fT 322 GHz occurs at VCB 0.27 V when the collector is partially undepleted for reduced transit time, and peakfmax 459 GHz occurs at VCB 0.78 V when the collector is fully depleted and CBC is minimized. Figure 3 illustrates the major blocks of our static divider. Static divider design in the D-Band regime poses many challenges. First, transistors operating at such high frequencies in ECL topologies are prone to oscillation. Next, the time constants at the latch load nodes can limit high-speed performance. Capacitances from conventional, transistor current sources begin to become limiting time constants as well. The interface circuitry to and from the actual divider core must be carefully designed to not mask core performance. Input reflections and circuit bandwidth make it challenging for the input path to provide adequate power and slew rate to switch the core. Today, D-Band sources are single-ended, where headroom can also limit the maximum signal level delivered to the core. The divider core output must contend with the parasitic capacitance of the feedback path as well as the loading of subsequent output stages. Employing high bandwidth circuit techniques can sometimes be detrimental to low frequency performance, further exacerbating the challenge of static divider design. Finally, power must be considered for practical systems. Each of the mentioned challenges was addressed in the divider design. The divider was stabilized by covering most of the circuit with a ground plane. We found it to be a more optimal tradeoff between stability and bandwidth compared to other techniques, such as inserting damping resistors at base terminals. Inductive peaking was used to improve the time constant at the latch load nodes. Resistors were used for all current sources in the circuit to reduce current source capacitance. A broadband input matching network was designed and optimized to minimize reflections and maximize power delivered to the divider core. The layout floorplan of the divider core was such that the inter-latch signals are perpendicular to the main divider signal flow, resulting in a relatively short divider feedback interconnect path. Relatively large resistances were inserted between the core and output stages to alleviate core capacitive loading. Careful selection and iterative evaluation of devices, resistors, and inductances was required to achieve simultaneous high and low frequency performance, i.e., static performance. We found emitter resistance to be a key device limiter in static performance. Power can be substantially reduced in a currentsteering latch topology by removing emitter followers (EF). However, this results in non-optimal base-collector biasing of the switching and regenerative latch pairs. Realizing that JE of the EF is the key for high frequency performance, the supply voltage on the EF was reduced while maintaining the same JE. This results in much lower power dissipation than if the EF were biased at the same supply voltage as the switching and regenerative pairs. Divider testing done in the V, W, and D-bands were done with a diode quadrupler or backward-wave oscillator (BWO) and harmonic mixers. A conventional RF signal generator was used for testing at 50 GHz and below. Measured divider performance is illustrated at 154.75 GHz and 5 GHz in Figure 4 and Figure 5, respectively. Our 154.75 GHz device was damaged during testing so we were only able to obtain a sensitivity plot from another site in the same wafer that operated from 10 GHz to 151 GHz (see Figure 6).