Performance of spin-based current-gating devices

Abstract

Michael E. Flatte* and Kimberley C. Hall** *Department of Physics and Astronomy, University of Iowa, Iowa City, IA 52242 USA Phone:+1-319-335-0201, Fax:+1-319-353-1115, Email: michael_flatte(mailaps.org **Department of Physics, Dalhousie University, Halifax, Nova Scotia B3H 4R2 Canada Phone:+1 -902-494-7109, Fax:+1 -902-494-5191, Email: Kimberley.Hall(dal.ca We have compared the fundamental limits of performance of an individual spin-based current-switching device with an individual charge-based current-switching device. All the contacts to each of the devices are assumed to be incoherent"; no quantum mechanical phase relation is maintained by electrons in the contact regions. We find that the use of spin-encoded information within the spin-based current-switching device leads to dramatic improvements in dynamic and static power dissipation relative to charge-based devices, and bypasses current roadblocks to charge device scaling. This includes a lower threshold voltage and lower capacitance than on the semiconductor roadmap for field effect transistors for logic through 2018. The charge-based current switching numbers for comparison have been taken from the semiconductor roadmap[l], which provides targets for complementary metal oxide semiconductor (CMOS) field-effect transistors (FETs) over the next 15 years. As the interest here is on low power dissipation, the focus of the comparison will be on the low standby power (LSTP) branch of the roadmap. The elements of transistor power dissipation examined include the leakage current and gate switching energies, gate switching speed, sourcedrain saturation current, and gate capacitance. In this analysis any benefit of coupled spin-based transistors is neglected (e.g. the design of a spin-based circuit to act as an XOR gate). A controllable spin lifetime forms the basis for transistor action in the device we consider[2]. Once polarized spins (to be specific, spin-up) have been injected into a channel, either from a magnetic material or using a nonmagnetic spin filter, their motion through the device can be controlled according to whether they remain spin polarized or not. If they remain spin polarized, and the drain contact spin filter only accepts spin-down carriers, then current does not flow from source to drain. This is the situation when no electric field is applied using the gate contact. When an electric field is applied then the spin polarization decays rapidly in the channel. In this situation current flows easily from source to drain. So in this design there is no moveable barrier between source and drain. The spin-dependent barriers in this device permit carriers of one spin orientation to pass while preventing those of the other spin polarization. These barriers are not raised or lowered. The source-drain current is proportional to the spin relaxation rate, so for a 10 ps spin lifetime in the "on" state and a 105 on-off ratio the spin lifetime must be 1 Fis in the off state (100 Fis for a 107 on-off ratio). Spin lifetimes in excess of 150 ns have been observed experimentally in bulk GaAs[3], so the 1 Fis value "off' value was used. It only requires an average 0.1 meV spin splitting (associated with a random effective magnetic field direction) to cause a spin to relax within 10 ps. This spin splitting is not generated directly by the gate voltage, but is induced by the applied electric field and the spin-orbit interaction of the material. For a 200A thick InAs quantum well the electric field to reduce the spin lifetime to 10 ps at room temperature is 50kV/cm. Thus the threshold voltage is 100 mV, a factor of 4 less than the LSTP CMOS value of 400 mV. It can be reduced further if a material with a larger spin-orbit interaction than InAs (such as InSb or an InAs/GaSb superlattice) is used. The other quantity entering the dynamic power dissipation (power-delay product) is the gate capacitance, from Cg =ocsA/D, where c0 is the dielectric permittivity of vacuum, c, the relative dielectric constant of the semiconductor, A the area of the gate and D the thickness of the region the electric field is applied to. In CMOS the thickness of the oxide layer determines D, whereas for the spin transistor the quantum well thickness determines D. For a spin transistor gate of the same area as a CMOS gate the gate capacitance is thus a factor of 5 smaller. The threshold voltage and the gate capacitance indicates that the dynamic power dissipation would be a factor of 500 times smaller for the spin transistor than LSTP CMOS in 2018. The other important form of power dissipation is the static power dissipation. In CMOS the dominant source of static power dissipation is the source-drain leakage current. The target value for 2018 LSTP CMOS is 100 pA/rm. In the spin transistor the dominant source is the spin relaxation in the "off' state. For the gate length target in 2018 LSTP CMOS of 10 nm, a quantum well doping of 2 1012 cm2, and a 1 Fis spin relaxation time, the leakage current for the spin transistor will be 16 pA/rm, a factor of 6 smaller than for 2018 LSTP CMOS The switching speed is also an important metric, and depends on the source-drain current in the "on" state, the threshold voltage and the gate capacitance. For a 10 ps "on" spin relaxation time and the parameters above, the switching time will be 3 ps, 10 times longer than the target for 2018 LSTP CMOS. Increasing the carrier doping level in the quantum well reduces the switching time, although it also increases the static leakage current. The switching time can be reduced without increasing the leakage current if the spin transistor quantum well uses a material with a larger spin-orbit interaction, such as InSb or InAs/GaSb superlattices. [1] International Technology Roadmap for Semiconductors San Jose, CA: Semiconductor Industry Association, 2003 [online] Available: http://public.itrs.net [2] K. C. Hall et al., Appl. Phys. Lett. 83, 2937 (2003).