Optimal Spacing of Carbon Nanotubes in a CNFET Array for Highest Circuit Performance

Carbon Nanotube field effect transistors (CNFETs) have appeared as very promising alternatives to traditional Si MOSFETs. It has often been argued, mostly qualitatively, that single CNT transistors would not be useful for VLSI, and one needs to have transistor arrays to get sufficient current out of them particularly to drive fixed capacitive loads. In this paper we investigate the optimal spacing of carbon nanotubes in an array for the highest performance. The CNFET that we have used in our analyses are Schottky Barrier CNFETs (Fig. la) with mid-gap Source/Drain work function, 20nm ballistic channel, a planar top gate with a 2nm thick HfO2 dielectric. It works on the principle of barrier thickness modulation by a gate voltage and carrier tunneling through the Schottky barrier (Fig. lb). The simulation methodology for CNFETs using NEGF as described in [2] has been used in this paper. To estimate the coupling between nanotubes, Poisson Equation is solved in 3D for arrays of CNTs. End effects have been neglected. The numerical I-V and C-V data have been imported to a circuit simulator and solved. Fig. 2a illustrates the top gate structure and Fig. 2b illustrates how the charge is distributed on the gate, for different T0x For high performance it is imperative to use well controlled growth processes where one would be able to synthesize an array of parallel carbon nanotubes with proper source/drain and gate structures. Let us consider a width of 100nm where CNTs of diameter d and inter-nanotube spacing, S need to be laid out in the form of an array (Fig. 3a). Let us consider that this transistor is driving an identical transistor. From a device design perspective, the optimal spacing S has been proposed to be approximately two times the CNT diameter (S=2d) [3] or S=2d + 4T0,. [4]. However, a circuit level analysis should also incorporate the role of parasitic and load capacitances. The parasitics (like the gate overlap or contact) scale with the transistor width, whereas pin and interconnect capacitances do not. We have two cases to consider: 1. Intrinsic load case: On one hand we can only have the intrinsic load capacitance corresponding to a CNFET driving another CNFET. This includes the device capacitance and is proportional to the number of tubes N. The delay of such a transistor can be simplified to: Low(CEXT PER TUBE X No. of Tubes)VDD (CPER TUBE )DD LwLOAD TPEP x No.ofTubes I (1) ION IPER TUBE X No. of Tubes IPER TUBE