Elemental devices for monolithic optoelectronic integrated circuits on lattice-matched Si/III-V-N/Si structure

Abstract

Optoelectronic integrated circuits (OEICs) have been expected for realization of novel devices and circuits. It is necessary for realization of OEICs to combine Ill-V compounds and Si with high quality. However, many dislocations were induced by the large difference in valence electron and lattice-constant between Ill-V compounds, such as GaAs and InP, and Si. We have already realized a dislocation-free and lattice-matched Si/GaPN/Si using molecular beam epitaxy (MBE)[1]. In addition, a dislocation-free InGaPN/GaPN double hetero (DH) light emitting diode (LED) has been realized on a Si substrate[2]. If these technologies are merged systematically, the top Si layer and III-V-N alloys will be used for integrated circuits and optical devices, respectively, as shown in Fig. 1 [3]. In this study, we have investigated a fabrication process for monolithic OEICs based on Si/III-V-N/Si structure and realized MOSFETs and LEDs in the same Si/III-V-N/Si wafer. A Si/III-V-N/Si wafer was grown by MBE, as shown in Fig. 2. A p-Si(100) substrate misoriented 40 toward [011] direction with carrier concentration of 5x1 OI8cm3 was used as a substrate. A GaP layer grown by migration enhanced epitaxy (MEE) is necessary to solve the difference in valence electron between Si and Ill-V compound semiconductors. An InyGa1-yPO.96No.04/GaPo.98No.o2 DH structure was grown at 500°C in the III-V-growth chamber. The GaP098N002 layers are lattice matched to Si. InyGa1 yP0.96No.04 layer is an active layer for DH LEDs. After the growth of DH structure, a thermal treatment was performed at 450°C and the sample was transferred to the Si-growth chamber through a vacuum chamber. A 1 ptm-thick Si layer was grown by electron-beam evaporator on the n-GaPN layer. A carrier concentration in the Si epilayer of 4x1017cm-3 was measured by four-point probe method. A fabrication sequence is proposed in Fig. 3. A 1ptm-thick field-oxide layer was deposited by chemical vapor phase deposition after separating LED regions by reactive ion etching. For simplicity of the process, a thermal annealing to increase the luminescence efficiency and a post-annealing of ion-implantation were combined with a gate-oxidation process. The luminescence of GaPN layers has been increased by the annealing at 900°C for 1-10min[4]. Thus, gate-oxidation was performed at 900°C for 10min in a wet 02 ambient, since a growth rate is higher than that in dry oxidation. Figure 4 shows a micrograph of a chip fabricated through the OEIC process. pMOSFETs and LEDs are shown in the same chip. Capacitance-voltage characteristics of MOS diodes showed surface inversion. The thickness of gate oxide was estimated at 16nm, which was close to a thickness of oxide grown on a bare n-Si wafer as a reference. The carrier concentration was estimated at 6.6x1 017cm-3. The wet oxidation was found to be utilized for the OEIC process. Figure 5(a) shows typical characteristics of drain currents(IdS) versus drain voltages(Vd,). Although a threshold voltage of -3.1V was relatively high, the pMOSFET characteristics have been obtained on the OEIC wafer for the first time. It is necessary to improve the growth process for reducing the threshold voltage and carrier concentration in Si epilayer, which could be caused by incorporation of P atoms during the growth. The InGaPN/GaPN DH LEDs in Fig. 4 showed electroluminescence at room temperature, as shown in Fig.5(b). Red luminescence of 2Ox45 im2 LED was also found by visual observation even at a current of 800tA. The properties ofLEDs will be investigated in detail. In conclusion, we have realized the elemental devices for monolithic OEICs on the lattice-matched Si/III-V-N/Si structures by the proposed OEIC process. This work was partially supported by the Ministry of Education, Science, Sports and Culture (Specially Promoted Research and the 21st Century COE Program).