氮化镓衬底上HfO2和硅界面钝化的耗尽型MOSFET

I. Ok, H. Kim, M. Zhang, T. Lee, F. Zhu, G. Thareja, L. Yu, S. Koveshnikov, W. Tsai, V. Tokranov, M. Yakimov, S. Oktyabrsky, Jack C. Lee
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PVD HfO2 films were deposited using the modulation technique [1], followed by PDA at 600°C in N2 (02 5%). Fig. 1 shows transmission electron microscopy (TEM) on the MOSCAP with 10nm HfO2 with PDA of 600°C 3 min. The interface between HfO2 and GaAs surface was degraded severely after 600°C 3 min PDA for sample without Si ICL. Electron energy loss spectroscopy (EELS) shows that Si was partially oxidized simply due to exposure to air after Hf deposition process (Fig. 2). In Fig. 3 and Fig. 4 TEM, EELS and energy dispersive X-ray spectroscopy (EDXS) show that after Imin Si ICL deposition, the interface Si changed to SiO2 with increasing PDA time or temperature while protecting GaAs surface. ICL thickness also changed. X-ray photoelectron spectroscopy (XPS) also show similar result in that with 1 min Si deposition time, Si was partially oxidized, and after Imin PDA in N2(O2 50 o), the Si ICL was oxidized to SiO2 (Fig. 5). However, if 2min Si ICL thickness was used, Si was not fully oxidized even after 15min PDA at 600°C (Fig. 6). Fig. 7 and Fig. 8 summarize the frequency dispersion characteristics (AV and 00 are defined in Fig. 7) versus Si ICL deposition condition as a function of PDA time for capacitor. With appropriate thickness of Si ICL, low frequency dispersion (< 50/O) can be obtained. In contrast, without Si ICL, frequency dispersion was around 25%. In general, Si deposition time of 60-100 second and longer PDA time resulted in reduced frequency dispersion. Frequency dispersion was more depended on Si deposition time than on PDA condition. The results suggest that there is negligible Fermi level pinning at the surface. Flat band voltage shift with different metal gate also provided good evidence for unpinned Fermi level (Fig. 9). Si deposition time of 60 second with 7min PDA time resulted in lower DA value using conductance method (Fig. 10). Fig. 11 demonstrates the linear dependence of the equivalent oxide thickness (EOT) on the physical thickness of HfO2. The k-value of the gate HfO2 was found to be k=19.5 (with ksIo2 = 3.9) [2]. Leakage current was reduced (to _10-5 A/cm2) by using the Si ICL for 4.Onm thick high-k dielectric in N-type GaAs wafer (Fig. 12). We have demonstrated depletion mode MOSFET using the optimum thickness and PDA condition (1 min Si deposition time (z 0.8-Inm) and 7min PDA) of the Si passivation layer. The schematic cross section and top view (ring-type) of depletion mode GaAs MOSFET with Si passivation is shown in Fig. 13. The thickness of molecular beam epitaxy (MBE) grown n-type GaAs epi-layer layer on semi-insulating substrate was 40nm with Si dopant concentration in the epi-layer of 3x1017 cm-3. The Id-Vg characteristics are shown in Fig. 14. Depletion mode MOSFET with PVD Si passivation layer shows VT of -1.41V, excellent off-current loff of 69pA, transconductance Gmmax of 123gA/V and swing S of 113mV/dec with width 400pm and length 5pm at drain voltage (Vd) =5OmV. Electron mobility for GaAs MOSFET with PVD Si passivation was estimated to be 568cm2/Vs. Fig. 15. Fig. 16 show the Id-Vg characteristics that Id max =2.58 mA at Vg-Vth = 1 V. Electrical characteristics of TaN/HfO2/GaAs MOS capacitors with Si interface control layer (ICL) under various PDA condition and various Si deposition temperature/time was presented. We have demonstrated depletion mode MOSFETs. Excellent electrical characteristics with thin EOT (-2nm), low frequency dispersion (<50/O) and high maximum mobility (568 cm2/V-s) have been obtained.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"616 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Depletion-Mode MOSFET on n-GaAs substrate with HfO2 and Silicon Interface Passivation\",\"authors\":\"I. Ok, H. Kim, M. Zhang, T. Lee, F. Zhu, G. Thareja, L. Yu, S. Koveshnikov, W. Tsai, V. Tokranov, M. Yakimov, S. Oktyabrsky, Jack C. Lee\",\"doi\":\"10.1109/DRC.2006.305112\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High-k dielectrics, such as HfO2, have been considered as alternative to SiO2 in Si-based CMOS technology. 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Electron energy loss spectroscopy (EELS) shows that Si was partially oxidized simply due to exposure to air after Hf deposition process (Fig. 2). In Fig. 3 and Fig. 4 TEM, EELS and energy dispersive X-ray spectroscopy (EDXS) show that after Imin Si ICL deposition, the interface Si changed to SiO2 with increasing PDA time or temperature while protecting GaAs surface. ICL thickness also changed. X-ray photoelectron spectroscopy (XPS) also show similar result in that with 1 min Si deposition time, Si was partially oxidized, and after Imin PDA in N2(O2 50 o), the Si ICL was oxidized to SiO2 (Fig. 5). However, if 2min Si ICL thickness was used, Si was not fully oxidized even after 15min PDA at 600°C (Fig. 6). Fig. 7 and Fig. 8 summarize the frequency dispersion characteristics (AV and 00 are defined in Fig. 7) versus Si ICL deposition condition as a function of PDA time for capacitor. With appropriate thickness of Si ICL, low frequency dispersion (< 50/O) can be obtained. In contrast, without Si ICL, frequency dispersion was around 25%. In general, Si deposition time of 60-100 second and longer PDA time resulted in reduced frequency dispersion. Frequency dispersion was more depended on Si deposition time than on PDA condition. The results suggest that there is negligible Fermi level pinning at the surface. Flat band voltage shift with different metal gate also provided good evidence for unpinned Fermi level (Fig. 9). Si deposition time of 60 second with 7min PDA time resulted in lower DA value using conductance method (Fig. 10). Fig. 11 demonstrates the linear dependence of the equivalent oxide thickness (EOT) on the physical thickness of HfO2. The k-value of the gate HfO2 was found to be k=19.5 (with ksIo2 = 3.9) [2]. Leakage current was reduced (to _10-5 A/cm2) by using the Si ICL for 4.Onm thick high-k dielectric in N-type GaAs wafer (Fig. 12). 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引用次数: 2

摘要

在硅基CMOS技术中,高k介电体,如HfO2,被认为是SiO2的替代品。替代介质为考虑替代通道材料(如砷化镓)提供了极好的机会。在这项工作中,我们展示了具有Si接口控制层(ICL)的TaN/HfO2/GaAs MOS电容器在不同PDA(沉积后退火)条件下和不同Si沉积温度/时间下的电特性,以及在最佳电容条件下的耗尽模式MOSFET。获得了极薄EOT (-2nm)、低频色散(<50/O)和高最大迁移率(568 cm2/V-s)的优异电特性。采用Si溅射法制备了Si ICL。采用调制技术沉积PVD HfO2薄膜[1],然后在600°C N2(02.5%)中进行PDA。图1为含10nm HfO2的MOSCAP的透射电镜(TEM), PDA温度为600°C 3 min。对于不含Si ICL的样品,当PDA温度为600°C 3 min时,HfO2与GaAs表面之间的界面严重降解。电子能量损失谱(EELS)显示,在Hf沉积过程中,Si仅仅由于暴露在空气中而部分氧化(图2)。在图3和图4中,TEM、EELS和能量色散x射线谱(EDXS)显示,Imin Si ICL沉积后,随着PDA时间或温度的增加,界面Si变为SiO2,同时保护了GaAs表面。ICL厚度也发生了变化。x射线光电子能谱(XPS)也显示了类似的结果,在1分钟Si沉积时间,如果是部分氧化,和之后Imin PDA在N2 (O2 50 o),如果ICL的氧化是二氧化硅(图5)。然而,如果2分钟Si ICL厚度,如果没有完全氧化后15分钟PDA在600°C(图6)。图7和图8总结频率色散特性(AV和00在图7中定义)和Si ICL沉积条件的函数PDA电容器。适当厚度的硅ICL可以获得低频色散(< 50/O)。相比之下,没有Si ICL,频率色散在25%左右。一般来说,60-100秒的Si沉积时间和更长的PDA时间导致频率色散降低。频率色散对Si沉积时间的影响大于对PDA条件的影响。结果表明,表面存在可忽略不计的费米能级钉住。不同金属栅极的平带电压漂移也为非钉住费米能级提供了很好的证据(图9)。硅沉积时间为60秒,PDA时间为7min,电导法的DA值较低(图10)。图11显示了等效氧化物厚度(EOT)与HfO2物理厚度的线性关系。栅极HfO2的k值为k=19.5(其中ksIo2 = 3.9)[2]。通过使用4的Si ICL,泄漏电流降低(至_10-5 A/cm2)。n型GaAs晶圆中Onm厚高k介电体(图12)。我们已经证明了损耗模式MOSFET使用最佳厚度和PDA条件(1分钟Si沉积时间(z 0.8-Inm)和7min PDA)的Si钝化层。图13所示为Si钝化的耗尽型GaAs MOSFET的示意图截面和俯视图(环型)。在半绝缘衬底上生长n型GaAs外延层的分子束外延(MBE)厚度为40nm,外延层Si掺杂浓度为3x1017 cm-3。Id-Vg特性如图14所示。具有PVD Si钝化层的耗尽型MOSFET在漏极电压(Vd) =5OmV时,VT为-1.41V, off-current loff为69pA,跨导Gmmax为123gA/V,摆幅S为113mV/dec,宽度为400pm,长度为5pm。经PVD Si钝化的GaAs MOSFET的电子迁移率估计为568cm2/Vs。图15所示。图16显示了在Vg-Vth = 1 V时,Id max =2.58 mA的Id- vg特性。研究了具有Si界面控制层(ICL)的TaN/HfO2/GaAs MOS电容器在不同PDA条件和不同Si沉积温度/时间下的电学特性。我们已经演示了耗尽型mosfet。获得了极薄EOT (-2nm)、低频色散(<50/O)和高最大迁移率(568 cm2/V-s)的优异电特性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Depletion-Mode MOSFET on n-GaAs substrate with HfO2 and Silicon Interface Passivation
High-k dielectrics, such as HfO2, have been considered as alternative to SiO2 in Si-based CMOS technology. The alternative dielectrics provide excellent opportunity for considering alternative channel materials such as GaAs. In this work, we present the electrical characteristics of TaN/HfO2/GaAs MOS capacitors with Si interface control layer (ICL) under various PDA (post-deposition anneal) condition and various Si deposition temperature/time and depletion mode MOSFET using optimum capacitance condition. Excellent electrical characteristics with thin EOT (-2nm), low frequency dispersion (<50/O) and high maximum mobility (568 cm2/V-s) have been obtained. Si ICL was deposited by sputtering of Si. PVD HfO2 films were deposited using the modulation technique [1], followed by PDA at 600°C in N2 (02 5%). Fig. 1 shows transmission electron microscopy (TEM) on the MOSCAP with 10nm HfO2 with PDA of 600°C 3 min. The interface between HfO2 and GaAs surface was degraded severely after 600°C 3 min PDA for sample without Si ICL. Electron energy loss spectroscopy (EELS) shows that Si was partially oxidized simply due to exposure to air after Hf deposition process (Fig. 2). In Fig. 3 and Fig. 4 TEM, EELS and energy dispersive X-ray spectroscopy (EDXS) show that after Imin Si ICL deposition, the interface Si changed to SiO2 with increasing PDA time or temperature while protecting GaAs surface. ICL thickness also changed. X-ray photoelectron spectroscopy (XPS) also show similar result in that with 1 min Si deposition time, Si was partially oxidized, and after Imin PDA in N2(O2 50 o), the Si ICL was oxidized to SiO2 (Fig. 5). However, if 2min Si ICL thickness was used, Si was not fully oxidized even after 15min PDA at 600°C (Fig. 6). Fig. 7 and Fig. 8 summarize the frequency dispersion characteristics (AV and 00 are defined in Fig. 7) versus Si ICL deposition condition as a function of PDA time for capacitor. With appropriate thickness of Si ICL, low frequency dispersion (< 50/O) can be obtained. In contrast, without Si ICL, frequency dispersion was around 25%. In general, Si deposition time of 60-100 second and longer PDA time resulted in reduced frequency dispersion. Frequency dispersion was more depended on Si deposition time than on PDA condition. The results suggest that there is negligible Fermi level pinning at the surface. Flat band voltage shift with different metal gate also provided good evidence for unpinned Fermi level (Fig. 9). Si deposition time of 60 second with 7min PDA time resulted in lower DA value using conductance method (Fig. 10). Fig. 11 demonstrates the linear dependence of the equivalent oxide thickness (EOT) on the physical thickness of HfO2. The k-value of the gate HfO2 was found to be k=19.5 (with ksIo2 = 3.9) [2]. Leakage current was reduced (to _10-5 A/cm2) by using the Si ICL for 4.Onm thick high-k dielectric in N-type GaAs wafer (Fig. 12). We have demonstrated depletion mode MOSFET using the optimum thickness and PDA condition (1 min Si deposition time (z 0.8-Inm) and 7min PDA) of the Si passivation layer. The schematic cross section and top view (ring-type) of depletion mode GaAs MOSFET with Si passivation is shown in Fig. 13. The thickness of molecular beam epitaxy (MBE) grown n-type GaAs epi-layer layer on semi-insulating substrate was 40nm with Si dopant concentration in the epi-layer of 3x1017 cm-3. The Id-Vg characteristics are shown in Fig. 14. Depletion mode MOSFET with PVD Si passivation layer shows VT of -1.41V, excellent off-current loff of 69pA, transconductance Gmmax of 123gA/V and swing S of 113mV/dec with width 400pm and length 5pm at drain voltage (Vd) =5OmV. Electron mobility for GaAs MOSFET with PVD Si passivation was estimated to be 568cm2/Vs. Fig. 15. Fig. 16 show the Id-Vg characteristics that Id max =2.58 mA at Vg-Vth = 1 V. Electrical characteristics of TaN/HfO2/GaAs MOS capacitors with Si interface control layer (ICL) under various PDA condition and various Si deposition temperature/time was presented. We have demonstrated depletion mode MOSFETs. Excellent electrical characteristics with thin EOT (-2nm), low frequency dispersion (<50/O) and high maximum mobility (568 cm2/V-s) have been obtained.
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