I. Ok, H. Kim, M. Zhang, T. Lee, F. Zhu, G. Thareja, L. Yu, S. Koveshnikov, W. Tsai, V. Tokranov, M. Yakimov, S. Oktyabrsky, Jack C. Lee
{"title":"氮化镓衬底上HfO2和硅界面钝化的耗尽型MOSFET","authors":"I. Ok, H. Kim, M. Zhang, T. Lee, F. Zhu, G. Thareja, L. Yu, S. Koveshnikov, W. Tsai, V. Tokranov, M. Yakimov, S. Oktyabrsky, Jack C. Lee","doi":"10.1109/DRC.2006.305112","DOIUrl":null,"url":null,"abstract":"High-k dielectrics, such as HfO2, have been considered as alternative to SiO2 in Si-based CMOS technology. The alternative dielectrics provide excellent opportunity for considering alternative channel materials such as GaAs. In this work, we present the electrical characteristics of TaN/HfO2/GaAs MOS capacitors with Si interface control layer (ICL) under various PDA (post-deposition anneal) condition and various Si deposition temperature/time and depletion mode MOSFET using optimum capacitance condition. Excellent electrical characteristics with thin EOT (-2nm), low frequency dispersion (<50/O) and high maximum mobility (568 cm2/V-s) have been obtained. Si ICL was deposited by sputtering of Si. PVD HfO2 films were deposited using the modulation technique [1], followed by PDA at 600°C in N2 (02 5%). Fig. 1 shows transmission electron microscopy (TEM) on the MOSCAP with 10nm HfO2 with PDA of 600°C 3 min. The interface between HfO2 and GaAs surface was degraded severely after 600°C 3 min PDA for sample without Si ICL. Electron energy loss spectroscopy (EELS) shows that Si was partially oxidized simply due to exposure to air after Hf deposition process (Fig. 2). In Fig. 3 and Fig. 4 TEM, EELS and energy dispersive X-ray spectroscopy (EDXS) show that after Imin Si ICL deposition, the interface Si changed to SiO2 with increasing PDA time or temperature while protecting GaAs surface. ICL thickness also changed. X-ray photoelectron spectroscopy (XPS) also show similar result in that with 1 min Si deposition time, Si was partially oxidized, and after Imin PDA in N2(O2 50 o), the Si ICL was oxidized to SiO2 (Fig. 5). However, if 2min Si ICL thickness was used, Si was not fully oxidized even after 15min PDA at 600°C (Fig. 6). Fig. 7 and Fig. 8 summarize the frequency dispersion characteristics (AV and 00 are defined in Fig. 7) versus Si ICL deposition condition as a function of PDA time for capacitor. With appropriate thickness of Si ICL, low frequency dispersion (< 50/O) can be obtained. In contrast, without Si ICL, frequency dispersion was around 25%. In general, Si deposition time of 60-100 second and longer PDA time resulted in reduced frequency dispersion. Frequency dispersion was more depended on Si deposition time than on PDA condition. The results suggest that there is negligible Fermi level pinning at the surface. Flat band voltage shift with different metal gate also provided good evidence for unpinned Fermi level (Fig. 9). Si deposition time of 60 second with 7min PDA time resulted in lower DA value using conductance method (Fig. 10). Fig. 11 demonstrates the linear dependence of the equivalent oxide thickness (EOT) on the physical thickness of HfO2. The k-value of the gate HfO2 was found to be k=19.5 (with ksIo2 = 3.9) [2]. Leakage current was reduced (to _10-5 A/cm2) by using the Si ICL for 4.Onm thick high-k dielectric in N-type GaAs wafer (Fig. 12). We have demonstrated depletion mode MOSFET using the optimum thickness and PDA condition (1 min Si deposition time (z 0.8-Inm) and 7min PDA) of the Si passivation layer. The schematic cross section and top view (ring-type) of depletion mode GaAs MOSFET with Si passivation is shown in Fig. 13. The thickness of molecular beam epitaxy (MBE) grown n-type GaAs epi-layer layer on semi-insulating substrate was 40nm with Si dopant concentration in the epi-layer of 3x1017 cm-3. The Id-Vg characteristics are shown in Fig. 14. Depletion mode MOSFET with PVD Si passivation layer shows VT of -1.41V, excellent off-current loff of 69pA, transconductance Gmmax of 123gA/V and swing S of 113mV/dec with width 400pm and length 5pm at drain voltage (Vd) =5OmV. Electron mobility for GaAs MOSFET with PVD Si passivation was estimated to be 568cm2/Vs. Fig. 15. Fig. 16 show the Id-Vg characteristics that Id max =2.58 mA at Vg-Vth = 1 V. Electrical characteristics of TaN/HfO2/GaAs MOS capacitors with Si interface control layer (ICL) under various PDA condition and various Si deposition temperature/time was presented. We have demonstrated depletion mode MOSFETs. Excellent electrical characteristics with thin EOT (-2nm), low frequency dispersion (<50/O) and high maximum mobility (568 cm2/V-s) have been obtained.","PeriodicalId":259981,"journal":{"name":"2006 64th Device Research Conference","volume":"616 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Depletion-Mode MOSFET on n-GaAs substrate with HfO2 and Silicon Interface Passivation\",\"authors\":\"I. Ok, H. Kim, M. Zhang, T. Lee, F. Zhu, G. Thareja, L. Yu, S. Koveshnikov, W. Tsai, V. Tokranov, M. Yakimov, S. Oktyabrsky, Jack C. Lee\",\"doi\":\"10.1109/DRC.2006.305112\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High-k dielectrics, such as HfO2, have been considered as alternative to SiO2 in Si-based CMOS technology. The alternative dielectrics provide excellent opportunity for considering alternative channel materials such as GaAs. In this work, we present the electrical characteristics of TaN/HfO2/GaAs MOS capacitors with Si interface control layer (ICL) under various PDA (post-deposition anneal) condition and various Si deposition temperature/time and depletion mode MOSFET using optimum capacitance condition. Excellent electrical characteristics with thin EOT (-2nm), low frequency dispersion (<50/O) and high maximum mobility (568 cm2/V-s) have been obtained. Si ICL was deposited by sputtering of Si. PVD HfO2 films were deposited using the modulation technique [1], followed by PDA at 600°C in N2 (02 5%). Fig. 1 shows transmission electron microscopy (TEM) on the MOSCAP with 10nm HfO2 with PDA of 600°C 3 min. The interface between HfO2 and GaAs surface was degraded severely after 600°C 3 min PDA for sample without Si ICL. Electron energy loss spectroscopy (EELS) shows that Si was partially oxidized simply due to exposure to air after Hf deposition process (Fig. 2). In Fig. 3 and Fig. 4 TEM, EELS and energy dispersive X-ray spectroscopy (EDXS) show that after Imin Si ICL deposition, the interface Si changed to SiO2 with increasing PDA time or temperature while protecting GaAs surface. ICL thickness also changed. X-ray photoelectron spectroscopy (XPS) also show similar result in that with 1 min Si deposition time, Si was partially oxidized, and after Imin PDA in N2(O2 50 o), the Si ICL was oxidized to SiO2 (Fig. 5). However, if 2min Si ICL thickness was used, Si was not fully oxidized even after 15min PDA at 600°C (Fig. 6). Fig. 7 and Fig. 8 summarize the frequency dispersion characteristics (AV and 00 are defined in Fig. 7) versus Si ICL deposition condition as a function of PDA time for capacitor. With appropriate thickness of Si ICL, low frequency dispersion (< 50/O) can be obtained. In contrast, without Si ICL, frequency dispersion was around 25%. In general, Si deposition time of 60-100 second and longer PDA time resulted in reduced frequency dispersion. Frequency dispersion was more depended on Si deposition time than on PDA condition. The results suggest that there is negligible Fermi level pinning at the surface. Flat band voltage shift with different metal gate also provided good evidence for unpinned Fermi level (Fig. 9). Si deposition time of 60 second with 7min PDA time resulted in lower DA value using conductance method (Fig. 10). Fig. 11 demonstrates the linear dependence of the equivalent oxide thickness (EOT) on the physical thickness of HfO2. The k-value of the gate HfO2 was found to be k=19.5 (with ksIo2 = 3.9) [2]. Leakage current was reduced (to _10-5 A/cm2) by using the Si ICL for 4.Onm thick high-k dielectric in N-type GaAs wafer (Fig. 12). We have demonstrated depletion mode MOSFET using the optimum thickness and PDA condition (1 min Si deposition time (z 0.8-Inm) and 7min PDA) of the Si passivation layer. The schematic cross section and top view (ring-type) of depletion mode GaAs MOSFET with Si passivation is shown in Fig. 13. The thickness of molecular beam epitaxy (MBE) grown n-type GaAs epi-layer layer on semi-insulating substrate was 40nm with Si dopant concentration in the epi-layer of 3x1017 cm-3. The Id-Vg characteristics are shown in Fig. 14. Depletion mode MOSFET with PVD Si passivation layer shows VT of -1.41V, excellent off-current loff of 69pA, transconductance Gmmax of 123gA/V and swing S of 113mV/dec with width 400pm and length 5pm at drain voltage (Vd) =5OmV. Electron mobility for GaAs MOSFET with PVD Si passivation was estimated to be 568cm2/Vs. Fig. 15. Fig. 16 show the Id-Vg characteristics that Id max =2.58 mA at Vg-Vth = 1 V. Electrical characteristics of TaN/HfO2/GaAs MOS capacitors with Si interface control layer (ICL) under various PDA condition and various Si deposition temperature/time was presented. We have demonstrated depletion mode MOSFETs. Excellent electrical characteristics with thin EOT (-2nm), low frequency dispersion (<50/O) and high maximum mobility (568 cm2/V-s) have been obtained.\",\"PeriodicalId\":259981,\"journal\":{\"name\":\"2006 64th Device Research Conference\",\"volume\":\"616 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 64th Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2006.305112\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 64th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2006.305112","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Depletion-Mode MOSFET on n-GaAs substrate with HfO2 and Silicon Interface Passivation
High-k dielectrics, such as HfO2, have been considered as alternative to SiO2 in Si-based CMOS technology. The alternative dielectrics provide excellent opportunity for considering alternative channel materials such as GaAs. In this work, we present the electrical characteristics of TaN/HfO2/GaAs MOS capacitors with Si interface control layer (ICL) under various PDA (post-deposition anneal) condition and various Si deposition temperature/time and depletion mode MOSFET using optimum capacitance condition. Excellent electrical characteristics with thin EOT (-2nm), low frequency dispersion (<50/O) and high maximum mobility (568 cm2/V-s) have been obtained. Si ICL was deposited by sputtering of Si. PVD HfO2 films were deposited using the modulation technique [1], followed by PDA at 600°C in N2 (02 5%). Fig. 1 shows transmission electron microscopy (TEM) on the MOSCAP with 10nm HfO2 with PDA of 600°C 3 min. The interface between HfO2 and GaAs surface was degraded severely after 600°C 3 min PDA for sample without Si ICL. Electron energy loss spectroscopy (EELS) shows that Si was partially oxidized simply due to exposure to air after Hf deposition process (Fig. 2). In Fig. 3 and Fig. 4 TEM, EELS and energy dispersive X-ray spectroscopy (EDXS) show that after Imin Si ICL deposition, the interface Si changed to SiO2 with increasing PDA time or temperature while protecting GaAs surface. ICL thickness also changed. X-ray photoelectron spectroscopy (XPS) also show similar result in that with 1 min Si deposition time, Si was partially oxidized, and after Imin PDA in N2(O2 50 o), the Si ICL was oxidized to SiO2 (Fig. 5). However, if 2min Si ICL thickness was used, Si was not fully oxidized even after 15min PDA at 600°C (Fig. 6). Fig. 7 and Fig. 8 summarize the frequency dispersion characteristics (AV and 00 are defined in Fig. 7) versus Si ICL deposition condition as a function of PDA time for capacitor. With appropriate thickness of Si ICL, low frequency dispersion (< 50/O) can be obtained. In contrast, without Si ICL, frequency dispersion was around 25%. In general, Si deposition time of 60-100 second and longer PDA time resulted in reduced frequency dispersion. Frequency dispersion was more depended on Si deposition time than on PDA condition. The results suggest that there is negligible Fermi level pinning at the surface. Flat band voltage shift with different metal gate also provided good evidence for unpinned Fermi level (Fig. 9). Si deposition time of 60 second with 7min PDA time resulted in lower DA value using conductance method (Fig. 10). Fig. 11 demonstrates the linear dependence of the equivalent oxide thickness (EOT) on the physical thickness of HfO2. The k-value of the gate HfO2 was found to be k=19.5 (with ksIo2 = 3.9) [2]. Leakage current was reduced (to _10-5 A/cm2) by using the Si ICL for 4.Onm thick high-k dielectric in N-type GaAs wafer (Fig. 12). We have demonstrated depletion mode MOSFET using the optimum thickness and PDA condition (1 min Si deposition time (z 0.8-Inm) and 7min PDA) of the Si passivation layer. The schematic cross section and top view (ring-type) of depletion mode GaAs MOSFET with Si passivation is shown in Fig. 13. The thickness of molecular beam epitaxy (MBE) grown n-type GaAs epi-layer layer on semi-insulating substrate was 40nm with Si dopant concentration in the epi-layer of 3x1017 cm-3. The Id-Vg characteristics are shown in Fig. 14. Depletion mode MOSFET with PVD Si passivation layer shows VT of -1.41V, excellent off-current loff of 69pA, transconductance Gmmax of 123gA/V and swing S of 113mV/dec with width 400pm and length 5pm at drain voltage (Vd) =5OmV. Electron mobility for GaAs MOSFET with PVD Si passivation was estimated to be 568cm2/Vs. Fig. 15. Fig. 16 show the Id-Vg characteristics that Id max =2.58 mA at Vg-Vth = 1 V. Electrical characteristics of TaN/HfO2/GaAs MOS capacitors with Si interface control layer (ICL) under various PDA condition and various Si deposition temperature/time was presented. We have demonstrated depletion mode MOSFETs. Excellent electrical characteristics with thin EOT (-2nm), low frequency dispersion (<50/O) and high maximum mobility (568 cm2/V-s) have been obtained.