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Design of highly stable bandgap reference circuit for RF power harvester module of a 13.56 MHz smart card tag IC 13.56 MHz智能卡标签IC射频功率采集模块高稳定带隙参考电路设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368919
T. Adiono, Prasetiyo, S. Harimurti, Khilda Afifah, A. H. Salman
{"title":"Design of highly stable bandgap reference circuit for RF power harvester module of a 13.56 MHz smart card tag IC","authors":"T. Adiono, Prasetiyo, S. Harimurti, Khilda Afifah, A. H. Salman","doi":"10.1109/ISOCC.2017.8368919","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368919","url":null,"abstract":"Design of a temperature compensated and a highly stable bandgap voltage reference (BGR) circuit is presented in this paper. The design is used for power harvester in a 13.56 MHz smart card tag IC. In order to provide a high-power supply rejection ratio (PSRR) and wide range input supply, the bandgap reference circuit is enhanced by a pre-regulator circuit. The pre-regulator circuit is designed using differential amplifier to form a Low-dropout (LDO) regulator with a feedback to BGR core circuit. The pre-regulator circuit mainly improves the stability of output voltage when the input voltage changes. In bandgap core circuit, the reference voltage is obtained by compensating the negative temperature coefficient (CTAT) with a positive temperature coefficient (PTAT). Therefore, the output voltage can be kept stable when the temperature changes. Additionally, the start-up circuit is designed to overcome zero current condition in BGR circuit during the power starts on and this circuit turns off after the whole circuit reaches the desired operating point. This paper provides both the schematic and layout design implemented in 180nm CMOS technology. From the simulation result, the output voltage has a temperature coefficient of −0.26 mV/°C with temperature range from −50 °C to 125 °C and PSRR of −116 dB at DC with input voltage supply range of 1.8–6 V. The output voltage reference is stable around 1.143 V at the operating point region.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"7 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120862338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver 2.56 GSymbol/s MIPI C-PHY接收机的时钟恢复
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368876
J. Han, Pil-Ho Lee, Yeong-Woong Kim, Sang-Dong Kim, Jin-Woo Park, Young-Chan Jang
{"title":"A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver","authors":"J. Han, Pil-Ho Lee, Yeong-Woong Kim, Sang-Dong Kim, Jin-Woo Park, Young-Chan Jang","doi":"10.1109/ISOCC.2017.8368876","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368876","url":null,"abstract":"A 2.56 GSymbol/s receiver including clock recovery circuit is proposed for the mobile industry processor interface (MIPI) C-PHY version 1.0. The clock recovery circuit using a dynamic logic generates a clock signal sensing at least one transition among three received data. Furthermore, it removes a glitch noise generated due to the delay mismatch of three high-speed receivers using a deglitch circuit. The proposed C-PHY receiver including clock recovery circuit is implemented using a 0.11-μm CMOS process with a 1.2 V supply. The measured peak-to-peak time jitter of the recovered clock is approximately 17.5 ps at a date rate of 2.56 GSymbol/s.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121483251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A selector-based FFT processor and its FPGA implementation 基于选择器的FFT处理器及其FPGA实现
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368783
Yuya Hirai, Kazushi Kawamura, M. Yanagisawa, N. Togawa
{"title":"A selector-based FFT processor and its FPGA implementation","authors":"Yuya Hirai, Kazushi Kawamura, M. Yanagisawa, N. Togawa","doi":"10.1109/ISOCC.2017.8368783","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368783","url":null,"abstract":"Fast Fourier transform (FFT) is used in various applications such as signal processings and developing a high-speed FFT processor is quite required. In this paper, we propose a high-speed FFT processor based on selector logics. The selector-based FFT processor is constructed by focusing on the subtract-multiplication operations and partly applying selector logics to them. Furthermore, we implement the selector-based FFT processor on a Xilinx FPGA. Experimental results show that our proposed FFT processor can improve the processing speed by up to 21% and also reduce the number of LUTs by up to 33% compared with a naive FFT processor.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126997814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs 用于纳米瓦CMOS lsi的1.2 V, 33 ppm/°C, 40 nW，基于再生的BGR电路
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368794
Abhishek Shrivastava, Amandeep Kaur, M. Sarkar
{"title":"A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs","authors":"Abhishek Shrivastava, Amandeep Kaur, M. Sarkar","doi":"10.1109/ISOCC.2017.8368794","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368794","url":null,"abstract":"A regeneration based BGR circuit is proposed in this paper. The regeneration using positive feedback results in the positive temperature coeffecient of 2.34 mV/° C from the single stage at room temperature. This results in 60 % saving in power and over 80 % saving in area, when compared with the state-of-the-art trimming less BGR circuits. The obtained temperature coefficient is 33 ppm/° C for the temperature range 0° C–90° C. The circuit is designed and simulated in UMC 180nm CMOS process. The circuit consumes power of 40 nW and occupies an area of 0.003 mm2. The reference voltage of 819 mV is achieved at 1.2 V power supply. The power supply rejection ratio at 40 kHz is −47 dB.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128215247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a 400-MHz 1-V 1.4-mW CMOS RF receiver for MICS applications 用于MICS应用的400-MHz 1-V 1.4 mw CMOS RF接收器设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368866
Mihye Moon, Shinil Chang, Yongho Lee, Hyunchol Shin
{"title":"Design of a 400-MHz 1-V 1.4-mW CMOS RF receiver for MICS applications","authors":"Mihye Moon, Shinil Chang, Yongho Lee, Hyunchol Shin","doi":"10.1109/ISOCC.2017.8368866","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368866","url":null,"abstract":"This paper describes low-voltage and low-power design of a CMOS RF receiver front-end circuit for MICS applications. The direct-conversion RF receiver is composed of a single-ended cascode LNA, single-to-differential converting gm-stage, quadrature passive mixer with 25% LO duty cycle, and transimpedance amplifier. Extensive circuit simulations show that the receiver has the maximum conversion gain of 45 dB, the input-referred P1dB of −34.8 dBm, and the noise figure of 2.6 dB, while dissipating 1.4 mW from a 1-V supply.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132025324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Compact implementation IIR filter in FPGA for noise reduction of sensor signal 在FPGA中紧凑实现IIR滤波器，用于传感器信号的降噪
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368883
Koki Arauchi, Shohei Maki, Toshiyuki Inoue, A. Tsuchiya, K. Kishine
{"title":"Compact implementation IIR filter in FPGA for noise reduction of sensor signal","authors":"Koki Arauchi, Shohei Maki, Toshiyuki Inoue, A. Tsuchiya, K. Kishine","doi":"10.1109/ISOCC.2017.8368883","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368883","url":null,"abstract":"We have designed an infinite impulse response (IIR) filter aimed at reducing noise in systems that evaluate the status of parasympathetic activity. The IIR filter is implemented in a field programmable gate array (FPGA) with fewer components. As a result, compared with a finite impulse response (FIR) filter, which has equivalent frequency characteristics, there is a 69.7% reduction in processing time and the number of each element in the circuit is reduced by over 85.0%. By applying an IIR filter to the target system, the noise-related errors on the system are reduced while maintaining the same performance as that of an FIR filter.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123999176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An ultra-low-power 2.4 GHz receiver RF front-end employing a RF quadrature Gm-stage for Bluetooth low energy applications 超低功耗2.4 GHz接收器射频前端，采用射频正交通用级，适用于蓝牙低功耗应用
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368873
Sinyoung Kim, Taejong Kim, K. Kwon
{"title":"An ultra-low-power 2.4 GHz receiver RF front-end employing a RF quadrature Gm-stage for Bluetooth low energy applications","authors":"Sinyoung Kim, Taejong Kim, K. Kwon","doi":"10.1109/ISOCC.2017.8368873","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368873","url":null,"abstract":"In this paper, an ultra-low-power 2.4 GHz receiver RF front-end adopting a RF quadrature Gm-stage for Bluetooth low energy applications is proposed. The proposed quadrature Gm-stage in a mixer performs a single-to-differential conversion and minimizes power consumption of the LO path because the block generating quadrature signals such as a divider-by-2, a poly-phase filter and a quadrature voltage controlled oscillator are not required. The proposed quadrature Gm-stage adopting the gain and phase mismatch compensator generates adequate quadrature signals at 2.4 GHz. The prototype, realized in 65 nm CMOS process, achieves a conversion gain of 36 dB, a NF of 2.1 dB, and an IIP3 of −26 dBm while consuming 0.9 mA at supply voltage of 1 V.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124044898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new repair scheme for TSV-based 3D memory using base die repair cells 一种基于基模修复细胞的基于tsv的三维存储器修复方案
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368804
Donghyun Han, Hayoung Lee, Donghyun Kim, Sungho Kang
{"title":"A new repair scheme for TSV-based 3D memory using base die repair cells","authors":"Donghyun Han, Hayoung Lee, Donghyun Kim, Sungho Kang","doi":"10.1109/ISOCC.2017.8368804","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368804","url":null,"abstract":"In this paper, a new repair scheme which consists of a new repair algorithm and a base die structure of TSV based 3D memory is proposed. The traditional repair process in 3D memory uses extra cells in each memory layer. This paper proposes a new redundancy cell structure for repairing memory layers using spare cells on the base die which consists of solution memory, spare CAM and a control structure. The experimental results show that the repair rate of the new repair scheme is better than that of the inter-die method.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121045499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of asynchronous SAR ADC for low power mixed signal applications 低功率混合信号异步SAR ADC的设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368863
Deeksha Verma, Hye-Yeong Kang, Khuram Shehzad, M. R. Rehman, Kangyoon Lee
{"title":"Design of asynchronous SAR ADC for low power mixed signal applications","authors":"Deeksha Verma, Hye-Yeong Kang, Khuram Shehzad, M. R. Rehman, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368863","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368863","url":null,"abstract":"This paper presents a 10-bit, 8 MS/s Asynchronous SAR ADC with supply voltages of 1 V for low power mixed signal applications. The proposed asynchronous ADC consist of a comparator, SAR logic block and two control blocks (positive CDAC and Negative CDAC). The prototype of the proposed Asynchronous SAR ADC is implemented in 55 nm CMOS process technology. It achieves ENOB of 9.765 bit with sampling frequency of 8MS/s, input range of 0.2–0.8 V and power consumption is 0.124 mW.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116125399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A high efficiency Digital PWMDC-DC converter using hybrid control technique for EH applications 基于混合控制技术的高效数字PWMDC-DC变换器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368853
Truong Thi Kim Nga, Hamed Abbasizadeh, Truong Van Cong Thuong, Kangyoon Lee
{"title":"A high efficiency Digital PWMDC-DC converter using hybrid control technique for EH applications","authors":"Truong Thi Kim Nga, Hamed Abbasizadeh, Truong Van Cong Thuong, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368853","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368853","url":null,"abstract":"We have proposed a DC-DC Converter with high efficiency for ultra-low power Energy Harvesting (EH) applications. To achieve the high efficiency while remaining the high accuracy, the control signal pulse width is generated digitally instead of analog as in the conventional DC-DC converter. The presented Digital Pulse Width Modulation (DPWM) DC-DC converter employs the hybrid control technique which consists of the counter based and the open delay locked loop based topology. The output range of this converter can be from 4.5V to 6V by using 3-bits control with the trimming step of 20 mV. The power conversion efficiency of the proposed converter is 93% at 500mA load. Our proposed buck DC-DC converter is realized with CMOS 0.18 μm technology with the die size of 1200 μm × 980 μm.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"1 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116771038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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