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2017 International SoC Design Conference (ISOCC)最新文献

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A new stochastic mutiplier for deep neural networks 一种新的深度神经网络随机乘法器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368820
Subin Huh, Joonsang Yu, Kiyoung Choi
{"title":"A new stochastic mutiplier for deep neural networks","authors":"Subin Huh, Joonsang Yu, Kiyoung Choi","doi":"10.1109/ISOCC.2017.8368820","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368820","url":null,"abstract":"An XNOR gate is the most commonly used multiplier in bipolar encoded stochastic deep neural networks, but it is not suitable due to the inaccuracy in processing near-zero values. In this paper, we introduce a novel circuit that multiplies near-zero values more accurately and assess its performance with MNIST and CIFAR-10. For the CIFAR-10 dataset, the use of the proposed multipliers gives accuracy of 60.59%, improving by 11.64%p over the XNOR multiplier implementation.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126718644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS 1-V - 3-mW 2.4 ghz分数n锁相环合成器设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368867
Yongho Lee, Seungsoo Kim, Hyunchol Shin
{"title":"Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS","authors":"Yongho Lee, Seungsoo Kim, Hyunchol Shin","doi":"10.1109/ISOCC.2017.8368867","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368867","url":null,"abstract":"A fractional-N PLL synthesizer is designed in 65 nm CMOS general process for Bluetooth low-energy applications. For low-power consumption, the PLL synthesizer is designed in a single 1-V supply. The tuning range of PLL Synthesizer is 1.9–2.7 GHz to cover the ISM band for 1/5-fRF sliding-IF receiver. The simulated VCO phase noises at 1 MHz offset are −110 and −120 dBc/Hz at 2.7 and 1.9 GHz, respectively. With a fast VCO frequency calibration process included, the total lock time of the synthesizer is 12 μs. The synthesizer dissipates 3 mW from 1 V supply voltage.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116685468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A design of ultra low power I2C synchronous slave controller with interface voltage level independency in 180 nm CMOS technology 基于180nm CMOS技术的超低功耗I2C同步从控制器设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368885
Imran Ali, SungHun Cho, Dong Gyu Kim, M. R. Rehman, Kangyoon Lee
{"title":"A design of ultra low power I2C synchronous slave controller with interface voltage level independency in 180 nm CMOS technology","authors":"Imran Ali, SungHun Cho, Dong Gyu Kim, M. R. Rehman, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368885","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368885","url":null,"abstract":"In this paper, an ultra low power I2C synchronous slave controller (I2CSSC) is presented for low data rate communication with a master device. An additional level shifter circuit at the SDA data IO and SCL clock input is integrated which makes it independent of the interface voltage levels of the master device. This circuit also isolates the slave device and protects it from high voltage spikes from master. The controller is designed with finite state machine (FSM) model in a synchronous fashion. The design is integrated in a pressure sensor for chip calibration and register configuration and it is fabricated with 180 nm CMOS technology. The I2CSSC occupies a very small area of 5712 μm2 and it requires only 650 gates for its implementation. The current consumption is upto 87 μΑ from 1.8 V power supply and it needs only 157 μ' power for its full operation. The measurement results verify the functional accuracy and rigorousness of the proposed design with all I2C operating modes.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125217200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap 一个四分之一速率的3分接DFE，用于4Gbps数据速率，基于第一个推测分接的开关容量
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368875
Gyunam Jeon, Yong-Bin Kim
{"title":"A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap","authors":"Gyunam Jeon, Yong-Bin Kim","doi":"10.1109/ISOCC.2017.8368875","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368875","url":null,"abstract":"This paper presents a quarter-rate 3-tap DFE design for 4Gbps data rate with switched-capacitors based 1st speculative tap. We propose a quarter-rate DFE to supplement a drawback of switched-capacitors based half-rate DFE. In the half-rate DFE, comparators have not only low input capacitances but also low transconductance (low sensitivity) in order to eliminate the first post-cursor. Therefore, the comparators need to have enough pull-down time to make an accurate decision for a bit. The quarter-rate DFE approach has advantages of enough pull-down time because of operating at lower frequency of each data path and widely opened eye diagram at the output. In addition, it consumes less power than the half-rate DFE. The DFE is simulated with 180nm technology node and 1.8V power supply. The S21 parameter (channel loss) is 27 dB at 4 Gbps data rate, and the power consumption is 14.52 mW.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132709744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1.5-Gb/s equalizer with adaptive swing controller for TFT-LCD driver TFT-LCD驱动的1.5 gb /s均衡器和自适应摆幅控制器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368878
Yen-Chen Lin, Ching-Yuan Yang, James Chang
{"title":"A 1.5-Gb/s equalizer with adaptive swing controller for TFT-LCD driver","authors":"Yen-Chen Lin, Ching-Yuan Yang, James Chang","doi":"10.1109/ISOCC.2017.8368878","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368878","url":null,"abstract":"This paper presents a 1.5 Gb/s adaptive equalizer in a 0.18μm CMOS process. The adaptive loop with swing control technique is to generate swings that match the equalizer output swings. The proposed technique can improve the adaptation accuracy without using the conventional boost tuning techniques. Besides, the band-pass and low-pass filters in the adaption loop are all made up by active circuit in order to achieve lower chip area and power consumption. The measured eye widths of 1.5 Gb/s, and 0.75 Gb/s data are 0.18, and 0.075 UI for 123-cm FR4 board, respectively. The core area is 0.28mm2 and power consumption is 46mW (including output buffer) at 1.5 Gb/s from a 1.8-V supply.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132931188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High performance pulse ring voltage controlled oscillator for Internet of Things 用于物联网的高性能脉冲环压控振荡器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368918
Aditya Dalakoti, Merritt Miller, F. Brewer
{"title":"High performance pulse ring voltage controlled oscillator for Internet of Things","authors":"Aditya Dalakoti, Merritt Miller, F. Brewer","doi":"10.1109/ISOCC.2017.8368918","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368918","url":null,"abstract":"This paper presents a low phase noise, low power, wide tuning range, small area pulse ring oscillator fabricated in inexpensive 130nm CMOS technology, suitable for the widescale internet of things market. The ring uses very non-linear Pulse gates instead of conventional inverters as buffers substantially reducing the impulse sensitivity function (ISF) and thus the phase noise. The timing signal is rising-edge and ground referenced, allowing the supply to be used as control voltage. Common mode supply noise is rejected by double inversion in every stage of of the pulse gate as well as insensitivity to pulse amplitude and width. Fabricated ring oscillators show a phase noise of −98.41 dBC/Hz at 1MHz offset for 1.872GHz oscillator at 2.94mW power consumption and −95.14dBC/Hz at 1MHz offset for 388MHz oscillator at 216uW power consumption. The oscillators have a tuning range of 388MHz to 2.455GHz.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123254210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Building block operating system for 3D stacked computer systems with inductive coupling interconnect 具有电感耦合互连的三维堆叠计算机系统的构建块操作系统
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368844
Shinsuke Hamada, Atsushi Koshiba, M. Namiki, H. Amano
{"title":"Building block operating system for 3D stacked computer systems with inductive coupling interconnect","authors":"Shinsuke Hamada, Atsushi Koshiba, M. Namiki, H. Amano","doi":"10.1109/ISOCC.2017.8368844","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368844","url":null,"abstract":"This paper describes the software system for the building block computing systems. The programs on the system are executed by the building block OS that manages configuration information of the 3D stacked chips and virtualizes the accelerators as the OpenCL functions. In addition, the OS controls the power supply of the chips implemented with SOTB (Silicon on Thin Box). This paper introduces the basic concepts and functions of the software systems for the building block computing systems.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121878705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Motion vector-based film mode detection for frame rate up-conversion 帧率上转换的基于运动矢量的电影模式检测
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368890
S. Cho, S. Yoon, Young Hwan Kim
{"title":"Motion vector-based film mode detection for frame rate up-conversion","authors":"S. Cho, S. Yoon, Young Hwan Kim","doi":"10.1109/ISOCC.2017.8368890","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368890","url":null,"abstract":"This paper proposes a novel film mode detection method to improve the accuracy of frame rate up-conversion (FRUC). The existing methods need to calculate the field differences which are not necessary for FRUC. Furthermore, they prone to miss a non-film mode because they focus on detecting representative film modes, e.g., 3:2/2:2 pull-down. To avoid calculating field differences in film mode detection, the proposed method utilizes motion vectors which are already obtained from the FRUC. Furthermore, to improve the accuracy of detecting a non-film mode, the proposed method defines several features which use the variation of motion vectors for each frame. Then, it compares with the patterns of film modes. The proposed method can detect a non-film mode with 89.15% detection accuracy and increases the accuracy up to 10.93% for film modes compared to benchmark methods.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114962606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of power-efficient class-D CMOS power amplifier with resistor feedback 具有电阻反馈的d类CMOS功率放大器的设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368816
Gyusub Won, Dongsoo Lee, SungHun Cho, Kangyoon Lee
{"title":"Design of power-efficient class-D CMOS power amplifier with resistor feedback","authors":"Gyusub Won, Dongsoo Lee, SungHun Cho, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368816","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368816","url":null,"abstract":"In this paper, we propose a power amplifier with improved Efficiency and compact structure by using Resistor Feedback Technique. CMOS Class-D Type Power Amplifier with wide output range is presented. The proposed design is implemented in 55 nm 1P6M CMOS process. The measured maximum output power of PA is 10 dBm with a PAE of 25.8 % from a 3-V supply.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122664725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-performance two-step lagrange interpolation technique for 4K UHD applications 4K超高清应用的高性能两步拉格朗日插值技术
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368888
Yunho Park, Youngmin Kim, Youngjoo Lee
{"title":"High-performance two-step lagrange interpolation technique for 4K UHD applications","authors":"Yunho Park, Youngmin Kim, Youngjoo Lee","doi":"10.1109/ISOCC.2017.8368888","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368888","url":null,"abstract":"In this paper, we present an advanced interpolation algorithm to up-scale high definition (HD) and full-HD streams to 4K ultra-HD (UHD) videos. The proposed method basically adopts the 4-point-based Lagrange interpolation. When the interpolated pixel value using Lagrange interpolation is invalid, the order Lagrange polynomial is reduced for selecting more reliable results. By removing the unwanted overshooting or undershooting values in the high-order interpolation results, as a result, the proposed algorithm achieves improved visual quality.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124212166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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