{"title":"1-V - 3-mW 2.4 ghz分数n锁相环合成器设计","authors":"Yongho Lee, Seungsoo Kim, Hyunchol Shin","doi":"10.1109/ISOCC.2017.8368867","DOIUrl":null,"url":null,"abstract":"A fractional-N PLL synthesizer is designed in 65 nm CMOS general process for Bluetooth low-energy applications. For low-power consumption, the PLL synthesizer is designed in a single 1-V supply. The tuning range of PLL Synthesizer is 1.9–2.7 GHz to cover the ISM band for 1/5-fRF sliding-IF receiver. The simulated VCO phase noises at 1 MHz offset are −110 and −120 dBc/Hz at 2.7 and 1.9 GHz, respectively. With a fast VCO frequency calibration process included, the total lock time of the synthesizer is 12 μs. The synthesizer dissipates 3 mW from 1 V supply voltage.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS\",\"authors\":\"Yongho Lee, Seungsoo Kim, Hyunchol Shin\",\"doi\":\"10.1109/ISOCC.2017.8368867\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fractional-N PLL synthesizer is designed in 65 nm CMOS general process for Bluetooth low-energy applications. For low-power consumption, the PLL synthesizer is designed in a single 1-V supply. The tuning range of PLL Synthesizer is 1.9–2.7 GHz to cover the ISM band for 1/5-fRF sliding-IF receiver. The simulated VCO phase noises at 1 MHz offset are −110 and −120 dBc/Hz at 2.7 and 1.9 GHz, respectively. With a fast VCO frequency calibration process included, the total lock time of the synthesizer is 12 μs. The synthesizer dissipates 3 mW from 1 V supply voltage.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368867\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368867","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS
A fractional-N PLL synthesizer is designed in 65 nm CMOS general process for Bluetooth low-energy applications. For low-power consumption, the PLL synthesizer is designed in a single 1-V supply. The tuning range of PLL Synthesizer is 1.9–2.7 GHz to cover the ISM band for 1/5-fRF sliding-IF receiver. The simulated VCO phase noises at 1 MHz offset are −110 and −120 dBc/Hz at 2.7 and 1.9 GHz, respectively. With a fast VCO frequency calibration process included, the total lock time of the synthesizer is 12 μs. The synthesizer dissipates 3 mW from 1 V supply voltage.
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