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2017 International SoC Design Conference (ISOCC)最新文献

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Memory efficient self guided image filtering 内存高效自引导图像滤波
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-07 DOI: 10.1109/ISOCC.2017.8368910
Pervaiz Kareem, Asim Khan, C. Kyung
{"title":"Memory efficient self guided image filtering","authors":"Pervaiz Kareem, Asim Khan, C. Kyung","doi":"10.1109/ISOCC.2017.8368910","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368910","url":null,"abstract":"In this paper we propose a memory efficient architecture for implementation of Guided Image Filter (GIF) in Field Programmable Gate Array (FPGA) when input and guide images are the same. To reduce memory requirement we propose to use intermediate coefficients (a and b in the algorithm) directly without taking the mean to generate the filtered output. As bit widths of these coefficients are very high, the memory requirement is reduced by 66.67% while maintaining the quality of output image.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124637576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A fully-digital phase modulator with phase calibration loop for high data-rate systems 用于高数据速率系统的带相位校准环路的全数字相位调制器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-07 DOI: 10.1109/ISOCC.2017.8368865
Yong-Chang Choi, Sang-Sun Yoo, Hyung-Joun Yoo
{"title":"A fully-digital phase modulator with phase calibration loop for high data-rate systems","authors":"Yong-Chang Choi, Sang-Sun Yoo, Hyung-Joun Yoo","doi":"10.1109/ISOCC.2017.8368865","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368865","url":null,"abstract":"This paper presents a digital phase modulator for wide bandwidth polar transmitters. It adopts a digital-to-time converter (DTC) and high-speed phase calibration loop that improves sampling rate for the same phase resolution. The DTC consists of a chain delay line with different delay cells to generate a small phase. A feedback loop based on a novel time-to-digital converter (TDC) nested inside the phase modulator sets the DTC output phase accurately across the range of input digital code as well as over process, voltage, and temperature. By using the TDC-based feedback loop, the proposed phase modulator can achieve high sampling rate and small phase resolution. The phase modulator achieves 0.72 degree phase resolution and 40 MS/s sampling rate while consuming 8 mW of power. This phase modulator is implemented in a 180 nm CMOS technology and occupies 0.3 mm2.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131788738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS bandgap voltage reference with current-control circuits for the extended operating temperature range 带电流控制电路的CMOS带隙基准电压，用于扩展工作温度范围
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368797
R. A. Zawawi, Nuha A. Rhaffor, S. Mohd, S. S. Hamid, A. A. Manaf, K. Sawada
{"title":"A CMOS bandgap voltage reference with current-control circuits for the extended operating temperature range","authors":"R. A. Zawawi, Nuha A. Rhaffor, S. Mohd, S. S. Hamid, A. A. Manaf, K. Sawada","doi":"10.1109/ISOCC.2017.8368797","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368797","url":null,"abstract":"A CMOS bandgap voltage reference (BGR) with current-control circuits (CCC) design is proposed and simulated using Silterra 0.13μm CMOS technology. The CCCs is designed to suppress the total current at lower and higher temperatures. The proposed BGR utilizes curvature-corrected current generators that compensate the output voltage variation in the extended temperature range. The proposed circuit generates an output voltage of 1.1833V with a variation of 329μV within the temperature range of −50°C to 125°C. With a 2.5 V supply voltage, the BGR circuit was verified able to save power consumption by 12.6% compared with a circuit without the CCC.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115131035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A SoC platform for emerging technologies 面向新兴技术的SoC平台
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368909
Yonatan Shoshan, Slava Yuzhaninov, N. Edri, Shay Harari, Yehuda Rudin, Y. Weizman, Itai Nadler, Nir Rosenberg, Benjamin Flom, Dotan Bechor, Gilad Morag, E. Grigoriants, Naftaly Blum, R. Daly, Maya Reuveni, A. Fish
{"title":"A SoC platform for emerging technologies","authors":"Yonatan Shoshan, Slava Yuzhaninov, N. Edri, Shay Harari, Yehuda Rudin, Y. Weizman, Itai Nadler, Nir Rosenberg, Benjamin Flom, Dotan Bechor, Gilad Morag, E. Grigoriants, Naftaly Blum, R. Daly, Maya Reuveni, A. Fish","doi":"10.1109/ISOCC.2017.8368909","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368909","url":null,"abstract":"A generic System on a Chip (SoC) platform implementation in TSMC HPM28 is presented. The SoC operates at 0.9V and frequencies up to 4 GHz. It occupies 16 mm2. The platform enables proof-of-concept for emerging technologies. Advanced methods for the design and verification of the must-have building blocks are also presented. SW-HW development and verification with Palladium© is discussed. The methods presented offer a simplifying approach to the realization of a complex SoC design.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124284958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power SerDes for high-speed on-chip networks 用于高速片上网络的低功耗服务器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368879
Dongjun Park, Junsub Yoon, Jongsun Kim
{"title":"A low-power SerDes for high-speed on-chip networks","authors":"Dongjun Park, Junsub Yoon, Jongsun Kim","doi":"10.1109/ISOCC.2017.8368879","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368879","url":null,"abstract":"This paper presents a 32:1 muxing and 1:32 demuxing serializer/deserializer (SerDes) for low-power on-chip networks. The proposed deserializer employs a digital clock and data recovery (CDR) and uses a multiplying delay-locked loop (MDLL) based frequency multiplier to provide a reference clock for the CDR. The proposed SerDes and MDLL, implemented in a 65 nm CMOS process, achieves a measured data rate of 3.52 Gbps while performing 32:1 parallel-to-serial multiplexing and 1:32 serial-to-parallel de-multiplexing conversion. It occupies an active area of 0.19 mm2 and consumes 14 mW of power.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117260805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A battery-connected all-digital capacitive DC-DC converter with load tracking controller 一个电池连接的全数字电容DC-DC转换器与负载跟踪控制器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368822
M. Bahry, M. El-Nozahi, E. Hegazi
{"title":"A battery-connected all-digital capacitive DC-DC converter with load tracking controller","authors":"M. Bahry, M. El-Nozahi, E. Hegazi","doi":"10.1109/ISOCC.2017.8368822","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368822","url":null,"abstract":"This paper presents an all-digital switched-capacitor DC-DC converter with a Switch Logic Controller and Optimizer (SLCO) that converts the battery voltage (3.6 V nominally) into an output voltage of 1V. The SLCO achieves the maximum efficiency while keeping the output voltage ripples and load regulation at minimum values. The SC converter is implemented in 0.13 μm CMOS technology using thick oxide I/O devices and achieves a maximum efficiency of 68% at power density of 0.12 W/mm2. The SC converter delivers up to 100 mA load current. Output voltage ripples and load regulation are less than 16 mV and 0.02 %/mA, respectively.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121044215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-power low-noise ultrasonic receiver front-end IC for medical imaging systems 一种用于医学成像系统的低功耗低噪声超声接收器前端集成电路
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368916
F. U. Putri, Hyouk-Kyu Cha
{"title":"A low-power low-noise ultrasonic receiver front-end IC for medical imaging systems","authors":"F. U. Putri, Hyouk-Kyu Cha","doi":"10.1109/ISOCC.2017.8368916","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368916","url":null,"abstract":"An ultrasonic receiver front-end interface IC for capacitive micromachined ultrasound transducer in medical imaging systems is presented in this work. The proposed receiver front-end IC is comprised of a low-noise preamplifier providing a transimpedance gain of approximately 103 dBohm, followed by a low-power time-gain-compensation amplifier with accurate programmable gain. An input referred noise current density of 380 fA/VHz is obtained in the front-end IC while consuming 1.28 mW at 1.5-V supply. The proposed IC is designed using 180 nm CMOS process and the overall area is 0.042 mm2.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127085275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of the XY2-100 protocol on low-cost microcontroller XY2-100协议在低成本单片机上的实现
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368782
Dinh Van Luan, N. Truong, Hyun Kim, Hyuk-Jae Lee
{"title":"Implementation of the XY2-100 protocol on low-cost microcontroller","authors":"Dinh Van Luan, N. Truong, Hyun Kim, Hyuk-Jae Lee","doi":"10.1109/ISOCC.2017.8368782","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368782","url":null,"abstract":"To communicate with a controller board, several deflection systems use the digital XY2-100 protocol which is not equipped on most microcontroller units (MCUs). This paper presents a solution to implement the XY2-100 protocol using an 8-bit low-cost AVR RISC Microcontroller. By taking full advantages of the processor and optimizing the parity bit computation code, the MCU sends the data at the speed up to 3.3 Mbits/s. The program is used to control a galvanometric scanner and this can further be used for various systems such as CNC and 3D printer machines.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125194923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel scheme for information hiding at physical layer of wireless communications 一种新的无线通信物理层信息隐藏方案
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368882
S. Dhabu, Chip-Hong Chang
{"title":"A novel scheme for information hiding at physical layer of wireless communications","authors":"S. Dhabu, Chip-Hong Chang","doi":"10.1109/ISOCC.2017.8368882","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368882","url":null,"abstract":"We present a new scheme for information hiding at the physical layer of a wireless communication system. A reconfigurable pulse shaping filter is used in our scheme to convey secret information to the intended receiver, without affecting the performance of the underlying communication system. Simulation results in AWGN and Rayleigh fading channel validate our scheme and illustrate its stealth, transparency and robustness.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122819515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Development of SoC virtual platform for IoT terminals based on OneM2M 基于OneM2M的物联网终端SoC虚拟平台开发
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368917
Hyoung-Ro Lee, Chi-Ho Lin, Ki-Hyuk Park, Won-Jong Kim, Han-Jin Cho
{"title":"Development of SoC virtual platform for IoT terminals based on OneM2M","authors":"Hyoung-Ro Lee, Chi-Ho Lin, Ki-Hyuk Park, Won-Jong Kim, Han-Jin Cho","doi":"10.1109/ISOCC.2017.8368917","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368917","url":null,"abstract":"This paper describes development of SoC virtual platform for IoT terminals based on OneM2M. SoC virtual platform can satisfy occurring requirements by the rapid growth of IoT such as time-to market, cost reduction, and quality improvement. We run IoT terminal AE on both real hardware and SoC virtual platform, and compared the results of execution to verify the efficiency of the SoC virtual platform. The above comparison results shows same results on both SoC virtual platform and real hardware. Therefore, flexible software development was possible on the SoC virtual platform without actual hardware, and it is developed in the same environment as the target board, so the software could be used immediately on the target board in the future.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"34 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114052683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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