{"title":"内存高效自引导图像滤波","authors":"Pervaiz Kareem, Asim Khan, C. Kyung","doi":"10.1109/ISOCC.2017.8368910","DOIUrl":null,"url":null,"abstract":"In this paper we propose a memory efficient architecture for implementation of Guided Image Filter (GIF) in Field Programmable Gate Array (FPGA) when input and guide images are the same. To reduce memory requirement we propose to use intermediate coefficients (a and b in the algorithm) directly without taking the mean to generate the filtered output. As bit widths of these coefficients are very high, the memory requirement is reduced by 66.67% while maintaining the quality of output image.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Memory efficient self guided image filtering\",\"authors\":\"Pervaiz Kareem, Asim Khan, C. Kyung\",\"doi\":\"10.1109/ISOCC.2017.8368910\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we propose a memory efficient architecture for implementation of Guided Image Filter (GIF) in Field Programmable Gate Array (FPGA) when input and guide images are the same. To reduce memory requirement we propose to use intermediate coefficients (a and b in the algorithm) directly without taking the mean to generate the filtered output. As bit widths of these coefficients are very high, the memory requirement is reduced by 66.67% while maintaining the quality of output image.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368910\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper we propose a memory efficient architecture for implementation of Guided Image Filter (GIF) in Field Programmable Gate Array (FPGA) when input and guide images are the same. To reduce memory requirement we propose to use intermediate coefficients (a and b in the algorithm) directly without taking the mean to generate the filtered output. As bit widths of these coefficients are very high, the memory requirement is reduced by 66.67% while maintaining the quality of output image.