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2017 International SoC Design Conference (ISOCC)最新文献

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A 10-Gb/s equalizer with digital adaptation 一个10 gb /s均衡器与数字适应
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368817
Jui-Cheng Hsiao, Dai-En Jhou, Tai-Cheng Lee
{"title":"A 10-Gb/s equalizer with digital adaptation","authors":"Jui-Cheng Hsiao, Dai-En Jhou, Tai-Cheng Lee","doi":"10.1109/ISOCC.2017.8368817","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368817","url":null,"abstract":"An equalizer using a digital adaptive algorithm is proposed to minimize hardware cost. The proposed algorithm uses two analog reference levels to detect the low-frequency and high-frequency components of the input amplitude, respectively. By monitoring the two reference levels, the proposed equalizer can tune its high-frequency gain to compensate the channel loss appropriately. This work has been fabricated in a 40-nm process, and the equalizer core circuit occupies 0.014 mm2 and consumes 10 mW from a 1-V supply.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133685558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multiple-output LDO regulator applying with constant feedback factor 采用恒反馈系数的多输出LDO稳压器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368848
H. Mo, Daejeong Kim
{"title":"Multiple-output LDO regulator applying with constant feedback factor","authors":"H. Mo, Daejeong Kim","doi":"10.1109/ISOCC.2017.8368848","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368848","url":null,"abstract":"A Multiple-output LDO regulator can be a good choice in embedded systems in terms of no cross regulation, and efficiency. A small feedback factor in LDO topology incurs slow settling time, resulting in large ripples in the time-multiplexing strategy. A new proposed topology enhances the settling time, and hence the ripples by incorporating the constant feedback.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130521504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A pipeline ROM-less DDFS using equal-division interpolation 使用等分割插值的流水线无rom DDFS
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368808
Tsung-Yi Tsai, Hsiang-Yu Shih, Chua-Chin Wang
{"title":"A pipeline ROM-less DDFS using equal-division interpolation","authors":"Tsung-Yi Tsai, Hsiang-Yu Shih, Chua-Chin Wang","doi":"10.1109/ISOCC.2017.8368808","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368808","url":null,"abstract":"A pipeline ROM-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed in this investigation. In order to get higher SFDR and faster clock rate, different segments with various interpolation equations are analyzed. 2nd-order parabolic equations with proper selection of coefficients based on hardware cost is utilized to transcend the limitation of SFDR. Thus, a 4-stage pipeline architecture is realized to achieve better clock speed. This work demonstrates the maximum SFDR for 102 dBc and the output frequency for 50 MHz using TSMC 0.18μm CMOS technology cell library.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115864393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An inductive-coupling link for 3-D Network-on-Chips 三维片上网络的电感耦合链路
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368841
J. Kadomoto, H. Amano, T. Kuroda
{"title":"An inductive-coupling link for 3-D Network-on-Chips","authors":"J. Kadomoto, H. Amano, T. Kuroda","doi":"10.1109/ISOCC.2017.8368841","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368841","url":null,"abstract":"An inductive-coupling link for 3-D network-on-chips (NoC) is presented. Inductively coupled coils allow high-speed wireless communication between stacked chips. 35-bit parallel input data are serialized and transmitted. Silicon measurements from test chips implementing transceiver circuits, in 65 nm SOI CMOS technology demonstrate 875 Mb/s operation.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123603626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A design of 10MHz/20MHz bandwidth baseband circuit with high performance of ACRR 一种10MHz/20MHz带宽的高性能ACRR基带电路设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368913
Kwan-Tae Kim, Sungjin Kim, Dongsoo Lee, Kangyoon Lee
{"title":"A design of 10MHz/20MHz bandwidth baseband circuit with high performance of ACRR","authors":"Kwan-Tae Kim, Sungjin Kim, Dongsoo Lee, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368913","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368913","url":null,"abstract":"This paper presents a 10MHz / 20MHz Wide-Bandwidth baseband circuit with two 3rd order Low-pass Filter for a multi-channel system. To avoid interference between channels, the baseband circuit was designed with the high performance of ACRR(adjacent channel rejection ratio) 70.2 dB at 30 MHz and 60 MHz, respectively. This baseband circuit has the dynamic gain range of 65 dB and the gain step is 1dB. The proposed circuit is designed with a power supply voltage of 1 V and a 65 nm CMOS process.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123752587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Instruction set extension and hardware acceleration for SVM application toward a vector processor 面向矢量处理器的支持向量机应用的指令集扩展和硬件加速
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368818
Yalong Pang, Jun Han, Jianmin Zeng, Yujie Huang, Xiaoyang Zeng
{"title":"Instruction set extension and hardware acceleration for SVM application toward a vector processor","authors":"Yalong Pang, Jun Han, Jianmin Zeng, Yujie Huang, Xiaoyang Zeng","doi":"10.1109/ISOCC.2017.8368818","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368818","url":null,"abstract":"This paper presents instruction set extension and hardware acceleration for SVM application toward a vector processor. Based on the nyuzi processor, we customize the corresponding hardware acceleration unit, namely, kernel function processing unit (KPU), both supporting the linear kernel function and radial basis function (RBF) kernel. This work we utilize the mask vector to realize the exponential computation, and the total RBF kernel is completed with only approximately 35 basic instructions. The design is synthesized with SMIC 65nm CMOS technology, requiring 887 equivalent kGates and the max frequency is 540MHz. The simulation results show that with KPU the cycles of SVM training is obviously decreased and speedup is 2.62.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121079077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a capacitor-less LDO with high PSRR for RF energy harvesting applications 用于射频能量收集应用的高PSRR无电容LDO设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368852
Danial Khan, Hamed Abbasizadeh, Zaffar Hayat Nawaz Khan, Young-Jun Park, Kangyoon Lee
{"title":"Design of a capacitor-less LDO with high PSRR for RF energy harvesting applications","authors":"Danial Khan, Hamed Abbasizadeh, Zaffar Hayat Nawaz Khan, Young-Jun Park, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368852","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368852","url":null,"abstract":"This paper presents a capacitor-less low-dropout (LDO) regulators with high power supply rejection ratio (PSRR) for powering RF energy harvesting applications. The band-gap reference (BGR) in the proposed LDO utilizes a current mode regulator to isolate the band-gap reference circuitry from supply variations and noise. The proposed LDO achieves a high post-layout simulated PSRR of −85.67dB at 1 kHz. The proposed LDO is implemented in a standard 180nm CMOS technology with the die size of 378μm × 390μm.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122694115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design of a high speed CMOS image sensor with a hybrid single-slope column ADC and a finite state machine 基于混合单斜柱ADC和有限状态机的高速CMOS图像传感器设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368786
Keunyeol Park, Minhyun Jin, S. Kim, Minkyu Song
{"title":"Design of a high speed CMOS image sensor with a hybrid single-slope column ADC and a finite state machine","authors":"Keunyeol Park, Minhyun Jin, S. Kim, Minkyu Song","doi":"10.1109/ISOCC.2017.8368786","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368786","url":null,"abstract":"In this paper, design of a CMOS Image sensor (CIS) with a hybrid single-slope ADC is presented. To obtain a small size and a high conversion rate CIS, no sampling capacitor structure is employed. This is implemented with a DC reference voltage and a single ramp generator. Further, by changing the input node of comparator, it reduces gain errors generated by a conventional 4-input comparator's differentia pair. The proposed hybrid ADC selects the resistor DAC's reference voltage controlled by a Finite State Machine(FSM), and converts the residual voltage with the single slope technique. Based on 1-Poly 5-Metal 90nm back side illuminated(BSI) CIS process, the chip satisfies 1920 × 1440 pixel resolution whose pitch is 1.4um and 1.75-Tr active pixel sensor(APS).","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122760412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A low voltage capacitor based current controlled sense amplifier for input offset compensation 一种用于输入偏置补偿的低压电容型电流控制感测放大器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368810
Y. Vani, N. Rani, R. Vaddi
{"title":"A low voltage capacitor based current controlled sense amplifier for input offset compensation","authors":"Y. Vani, N. Rani, R. Vaddi","doi":"10.1109/ISOCC.2017.8368810","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368810","url":null,"abstract":"With CMOS technology scaling, there is a significant increase in transistor threshold voltage mismatch and variations, which result in offset voltage in SRAM designs. A large offset voltage will enlarge SRAM bitline swing and negatively affect dynamic power consumption during a read operation, sensing decision correct rate and operation speed. This paper presents a low voltage capacitor based current controlled sense amplifier design for input offset compensation. The simulation results carried out in 90nm CMOS technology prove that the proposed offset compensation scheme can reduce the standard deviation of offset voltage by 4x compared to the conventional sense amplifier design with about 0.4%, 2.9% overheads in area and power respectively at 0.5 V.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"1940 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129301382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Security analysis of intelligent vehicles: Challenges and scope 智能汽车安全分析:挑战与范围
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368805
Madhusudan Singh, Shiho Kim
{"title":"Security analysis of intelligent vehicles: Challenges and scope","authors":"Madhusudan Singh, Shiho Kim","doi":"10.1109/ISOCC.2017.8368805","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368805","url":null,"abstract":"Intelligent Vehicle means vehicles communication with everything such as, in-vehicle, vehicle-to-device, vehicle to vehicle communication, vehicle to roadside unit (RSU), etc. In short, we can say that intelligent vehicle is a system that provides communication environment between vehicles to everything (objects). Due to everything communicating to vehicles, it generates a large amount of data. Data generation is fine with this technology but we need to make sure that these data are safely and securely communicated with their designated destination (right device or users). Privacy of users is another big challenge in intelligent vehicle system. In this article, we discuss the challenges of automotive security in hardware and software, and propose a security architecture for automotive security and also mention future research challenges in automotive cyber security. This paper presents a discussion on Internet oriented application specific secure automotive technology, services, visual aspect and challenges for intelligent vehicles in both academic and industry.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133983487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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