{"title":"一个10 gb /s均衡器与数字适应","authors":"Jui-Cheng Hsiao, Dai-En Jhou, Tai-Cheng Lee","doi":"10.1109/ISOCC.2017.8368817","DOIUrl":null,"url":null,"abstract":"An equalizer using a digital adaptive algorithm is proposed to minimize hardware cost. The proposed algorithm uses two analog reference levels to detect the low-frequency and high-frequency components of the input amplitude, respectively. By monitoring the two reference levels, the proposed equalizer can tune its high-frequency gain to compensate the channel loss appropriately. This work has been fabricated in a 40-nm process, and the equalizer core circuit occupies 0.014 mm2 and consumes 10 mW from a 1-V supply.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 10-Gb/s equalizer with digital adaptation\",\"authors\":\"Jui-Cheng Hsiao, Dai-En Jhou, Tai-Cheng Lee\",\"doi\":\"10.1109/ISOCC.2017.8368817\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An equalizer using a digital adaptive algorithm is proposed to minimize hardware cost. The proposed algorithm uses two analog reference levels to detect the low-frequency and high-frequency components of the input amplitude, respectively. By monitoring the two reference levels, the proposed equalizer can tune its high-frequency gain to compensate the channel loss appropriately. This work has been fabricated in a 40-nm process, and the equalizer core circuit occupies 0.014 mm2 and consumes 10 mW from a 1-V supply.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368817\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368817","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An equalizer using a digital adaptive algorithm is proposed to minimize hardware cost. The proposed algorithm uses two analog reference levels to detect the low-frequency and high-frequency components of the input amplitude, respectively. By monitoring the two reference levels, the proposed equalizer can tune its high-frequency gain to compensate the channel loss appropriately. This work has been fabricated in a 40-nm process, and the equalizer core circuit occupies 0.014 mm2 and consumes 10 mW from a 1-V supply.
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