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2017 International SoC Design Conference (ISOCC)最新文献

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Implemetation of image classification CNN using multi thread GPU 基于多线程GPU的CNN图像分类实现
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368904
Seong-Hyeon Han, Kwang-Yeob Lee
{"title":"Implemetation of image classification CNN using multi thread GPU","authors":"Seong-Hyeon Han, Kwang-Yeob Lee","doi":"10.1109/ISOCC.2017.8368904","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368904","url":null,"abstract":"This study implemented an image classification CNN using a multi-thread GPU. For the CNN, the CIFAR10 dataset was used, and the multi-thread GPU had 256 threads. Using the 256 threads limited to each layer, allocation and parallel processing were conducted. The image classification CNN took 807 ms for computation.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"500 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123058081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Image compression based on MR-CNN (Modified Region Convolutional Neural Network) 基于MR-CNN(修正区域卷积神经网络)的图像压缩
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368901
Seongmo Park, B. Choi, Kwang‐Il Oh, S. E. Kim, J. -. Lee, J. Lee, S. Kang
{"title":"Image compression based on MR-CNN (Modified Region Convolutional Neural Network)","authors":"Seongmo Park, B. Choi, Kwang‐Il Oh, S. E. Kim, J. -. Lee, J. Lee, S. Kang","doi":"10.1109/ISOCC.2017.8368901","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368901","url":null,"abstract":"The proposed algorithm describes compressed image processing based on the Modified Region Convolutional Neural Network (MR-CNN) method. An object extracting unit may classify each of the modified-regions into a background region or an object region on the basis of the degree of pixel changes in the respective set of the modified-regions. There is an efficient compression ratio that can classify an image with each parameter according to the object, text, and background images. The algorithm proposed in the paper improved compression ratio by 10.95% with no degradation compared to the JPEG, and HEVC standards.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121129292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of CAN — CAN FD bridge for in-vehicle network 车载网络CAN - CAN FD桥的设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368912
J. Oh, Jongjin Wi, Seung Eun Lee
{"title":"Design of CAN — CAN FD bridge for in-vehicle network","authors":"J. Oh, Jongjin Wi, Seung Eun Lee","doi":"10.1109/ISOCC.2017.8368912","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368912","url":null,"abstract":"In this paper, we propose the communication bridge circuit between controller area network (CAN) and controller area network with flexible data-rate (CAN FD) protocol for in-vehicle network. The bridge transmits the CAN and CAN FD, supporting the electronic control units (ECUs) in different communication protocol. The prototype of the CAN FD bridge controller is implemented on an Field Programmable Gate Array (FPGA). Experimental result using a hardware scope demonstrates the feasibility of our proposal.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126385796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers 用于20 gb /s PAM-4接收机的0.18 μm CMOS技术的高线性跨阻放大器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368880
Chih-Chen Peng, Jau‐Ji Jou, Tien-Tsorng Shih, Chien-Liang Chiu
{"title":"High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers","authors":"Chih-Chen Peng, Jau‐Ji Jou, Tien-Tsorng Shih, Chien-Liang Chiu","doi":"10.1109/ISOCC.2017.8368880","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368880","url":null,"abstract":"In this paper, a high-linearity transimpedance amplifier (TIA) with automatic gain control (AGC) was designed in 0.18-μm CMOS Technology. For 700-μA input current amplitude, the total harmonic distortion (THD) of the TIA can be below 5%. The bandwidth of the TIA is 7.29-GHz, and its input referred current density is about 23.6-pA/√Hz. The TIA can be used in 20-Gb/s four-level pulse amplitude modulation (PAM-4) optical receivers. The power dissipation of the chip is 37.8-mW, and the chip area is 0.307-mm2.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127090920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Internal circuit offset auto compensation current sensor for wireless power systems 无线电力系统内部电路偏移自动补偿电流传感器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368847
ByeongGi Jang, Seongjin Oh, Young-Jun Park, Kangyoon Lee
{"title":"Internal circuit offset auto compensation current sensor for wireless power systems","authors":"ByeongGi Jang, Seongjin Oh, Young-Jun Park, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368847","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368847","url":null,"abstract":"This paper, we implemented a method to compensate the internal offset in the instrumentation amplifier structure. The proposed current sensor is used in a wireless power transmitter where the input voltage is changed. In order to lower the input voltage, resistor dividing is performed at the input terminal of the amplifier. When a voltage offset occurs in the circuit using this input voltage, the closed-loop circuit is changed to the open-loop and the open-loop output is confirmed in the calibration circuit to compensate the voltage offset generated in the circuit. We implemented the current sensor within +5 % error rate of the output occurring in the amplifier and resistor. The current sensor is designed with a 180 nm BCD process and it converts 0 ∼ 1.8 V voltage output by sensing 0 ∼ 3 A current.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122262086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of second order continuous-time sigma delta modulator in LabVIEW 二阶连续时间σ δ调制器的LabVIEW建模
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368861
M. R. Rehman, B. S. Rikan, Deeksha Verma, Imran Ali, Kangyoon Lee
{"title":"Modeling of second order continuous-time sigma delta modulator in LabVIEW","authors":"M. R. Rehman, B. S. Rikan, Deeksha Verma, Imran Ali, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368861","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368861","url":null,"abstract":"This paper presents a modeling of second order continuous-time sigma delta modulator (CT-SDM) in LabVIEW. It utilizes powerful graphical programing environment offered by LabVIEW which results in an efficient and user friendly modeling of CT-SDM. It considers system non-idealities involved in CT-SDM thus providing accurate simulation. Design flexibility is provided through well-organized GUI. Simulation of CT-SDM is performed which achieve SNDR of 128.32 dB and ENOB 21.02 bits.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133607763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Distortion analysis for a DC-DC buck converter DC-DC降压变换器的失真分析
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368857
V. Sharma, H. Shrimali, J. N. Tripathi, Rakesh Malik
{"title":"Distortion analysis for a DC-DC buck converter","authors":"V. Sharma, H. Shrimali, J. N. Tripathi, Rakesh Malik","doi":"10.1109/ISOCC.2017.8368857","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368857","url":null,"abstract":"This paper presents design and harmonic distortion analysis using Volterra series for a 12 V to 1.2 V buck converter designed in the 180 nm BCD8 technology of STMicroelectronics. The series determines the closed-form equations for fundamental, second and third harmonics. From the analysis, the results are 96 %, 97 % and 90 % matched with the simulation results when the amplitude of the input ripple varies from 0 V to 1.8 V.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132697671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Energy efficient and high throughput transceiver design in the capacitive coupling mode exploring tunnel transistors for 3D ICs 探索三维集成电路隧道晶体管的电容耦合模式下的高能效和高吞吐量收发器设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368900
T. Nagateja, R. Vaddi
{"title":"Energy efficient and high throughput transceiver design in the capacitive coupling mode exploring tunnel transistors for 3D ICs","authors":"T. Nagateja, R. Vaddi","doi":"10.1109/ISOCC.2017.8368900","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368900","url":null,"abstract":"Designing high throughput and energy efficient CMOS transceivers for capacitive coupling interconnects in 3D ICs is a big challenge and involves trade-off. In this paper, steep slope characteristics of Tunnel FETs are exploited for designing energy efficient and high throughput transceivers for capacitive coupling mode interconnects. A TFET based transceiver design has been proposed taking the unique TFET device characteristics and the design achieves 26 GHz throughput and 0.33 pJ/bit energy consumption with pad dimension of 1.5×1.5 μm2 at 0.3 V.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131623936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.5-Gb/s adaptive equalizer with periodically embedded clock encoding for intra-panel interfaces 1.5 gb /s自适应均衡器，周期性嵌入时钟编码，用于面板内接口
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368877
Chia-Chi Liu, Ching-Yuan Yang
{"title":"A 1.5-Gb/s adaptive equalizer with periodically embedded clock encoding for intra-panel interfaces","authors":"Chia-Chi Liu, Ching-Yuan Yang","doi":"10.1109/ISOCC.2017.8368877","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368877","url":null,"abstract":"This paper presents an adaptive equalizer used for 1.5-Gb/s phase-locked loop (PLL)-based point-to-point (P2P) high-speed interface with periodically embedded clock encoding (PECE). The adaptive equalizer uses a spectrum-balancing technique to detect the loss of energy without using the regulating comparator. The power detector combines current steering circuits and a preamplifier circuit to enhance the voltage swing. Implemented by 0.18-um CMOS process, this equalizer consumes 14.9 mW (excluding the output buffers) at 1.5 Gb/s with an output swing of 400 mV (p-p). The core area occupied is 0.05 mm2 (including output buffers), and the measured output peak-to-peak jitter is below 0.2 UI. The equalizer achieves high-frequency compensation, small area, and low power consumption.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133106782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hybrid path-diversity-dominant output selection method for Network-on-Chip systems 片上网络系统的混合路径分集优势输出选择方法
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368801
Jindun Dai, Wenda Ma, Xin Jiang, Takahiro Watanabe
{"title":"Hybrid path-diversity-dominant output selection method for Network-on-Chip systems","authors":"Jindun Dai, Wenda Ma, Xin Jiang, Takahiro Watanabe","doi":"10.1109/ISOCC.2017.8368801","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368801","url":null,"abstract":"Networks-on-Chip (NoCs) offers considerable performance improvement to Chip Multi-Processors (CMPs). As the communication between processors on NoC increases, its system performance faces a severe challenge in congestion issues. Adaptive routing algorithm for NoCs provides a variety of path options, thus, it has fantastic potential to achieve better traffic distribution across the network by avoiding the congested regions. An excellent output selection method can realize the potential of adaptive routing algorithm as highly as possible. Therefore, designing an efficient output selection method is highly desirable. Conventional output selection methods only consider local information (buffer vacancy) or global information (path diversity) separately, which makes them difficult to spread traffic to different paths for load balance. In this paper, we propose an efficient output selection method integrating global information of path diversity and local information of buffer vacancy, to solve congestion problem in NoCs.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133247391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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