{"title":"探索三维集成电路隧道晶体管的电容耦合模式下的高能效和高吞吐量收发器设计","authors":"T. Nagateja, R. Vaddi","doi":"10.1109/ISOCC.2017.8368900","DOIUrl":null,"url":null,"abstract":"Designing high throughput and energy efficient CMOS transceivers for capacitive coupling interconnects in 3D ICs is a big challenge and involves trade-off. In this paper, steep slope characteristics of Tunnel FETs are exploited for designing energy efficient and high throughput transceivers for capacitive coupling mode interconnects. A TFET based transceiver design has been proposed taking the unique TFET device characteristics and the design achieves 26 GHz throughput and 0.33 pJ/bit energy consumption with pad dimension of 1.5×1.5 μm2 at 0.3 V.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Energy efficient and high throughput transceiver design in the capacitive coupling mode exploring tunnel transistors for 3D ICs\",\"authors\":\"T. Nagateja, R. Vaddi\",\"doi\":\"10.1109/ISOCC.2017.8368900\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Designing high throughput and energy efficient CMOS transceivers for capacitive coupling interconnects in 3D ICs is a big challenge and involves trade-off. In this paper, steep slope characteristics of Tunnel FETs are exploited for designing energy efficient and high throughput transceivers for capacitive coupling mode interconnects. A TFET based transceiver design has been proposed taking the unique TFET device characteristics and the design achieves 26 GHz throughput and 0.33 pJ/bit energy consumption with pad dimension of 1.5×1.5 μm2 at 0.3 V.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368900\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368900","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Energy efficient and high throughput transceiver design in the capacitive coupling mode exploring tunnel transistors for 3D ICs
Designing high throughput and energy efficient CMOS transceivers for capacitive coupling interconnects in 3D ICs is a big challenge and involves trade-off. In this paper, steep slope characteristics of Tunnel FETs are exploited for designing energy efficient and high throughput transceivers for capacitive coupling mode interconnects. A TFET based transceiver design has been proposed taking the unique TFET device characteristics and the design achieves 26 GHz throughput and 0.33 pJ/bit energy consumption with pad dimension of 1.5×1.5 μm2 at 0.3 V.
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