{"title":"用于高数据速率系统的带相位校准环路的全数字相位调制器","authors":"Yong-Chang Choi, Sang-Sun Yoo, Hyung-Joun Yoo","doi":"10.1109/ISOCC.2017.8368865","DOIUrl":null,"url":null,"abstract":"This paper presents a digital phase modulator for wide bandwidth polar transmitters. It adopts a digital-to-time converter (DTC) and high-speed phase calibration loop that improves sampling rate for the same phase resolution. The DTC consists of a chain delay line with different delay cells to generate a small phase. A feedback loop based on a novel time-to-digital converter (TDC) nested inside the phase modulator sets the DTC output phase accurately across the range of input digital code as well as over process, voltage, and temperature. By using the TDC-based feedback loop, the proposed phase modulator can achieve high sampling rate and small phase resolution. The phase modulator achieves 0.72 degree phase resolution and 40 MS/s sampling rate while consuming 8 mW of power. This phase modulator is implemented in a 180 nm CMOS technology and occupies 0.3 mm2.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A fully-digital phase modulator with phase calibration loop for high data-rate systems\",\"authors\":\"Yong-Chang Choi, Sang-Sun Yoo, Hyung-Joun Yoo\",\"doi\":\"10.1109/ISOCC.2017.8368865\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a digital phase modulator for wide bandwidth polar transmitters. It adopts a digital-to-time converter (DTC) and high-speed phase calibration loop that improves sampling rate for the same phase resolution. The DTC consists of a chain delay line with different delay cells to generate a small phase. A feedback loop based on a novel time-to-digital converter (TDC) nested inside the phase modulator sets the DTC output phase accurately across the range of input digital code as well as over process, voltage, and temperature. By using the TDC-based feedback loop, the proposed phase modulator can achieve high sampling rate and small phase resolution. The phase modulator achieves 0.72 degree phase resolution and 40 MS/s sampling rate while consuming 8 mW of power. This phase modulator is implemented in a 180 nm CMOS technology and occupies 0.3 mm2.\",\"PeriodicalId\":248826,\"journal\":{\"name\":\"2017 International SoC Design Conference (ISOCC)\",\"volume\":\"68 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2017.8368865\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2017.8368865","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A fully-digital phase modulator with phase calibration loop for high data-rate systems
This paper presents a digital phase modulator for wide bandwidth polar transmitters. It adopts a digital-to-time converter (DTC) and high-speed phase calibration loop that improves sampling rate for the same phase resolution. The DTC consists of a chain delay line with different delay cells to generate a small phase. A feedback loop based on a novel time-to-digital converter (TDC) nested inside the phase modulator sets the DTC output phase accurately across the range of input digital code as well as over process, voltage, and temperature. By using the TDC-based feedback loop, the proposed phase modulator can achieve high sampling rate and small phase resolution. The phase modulator achieves 0.72 degree phase resolution and 40 MS/s sampling rate while consuming 8 mW of power. This phase modulator is implemented in a 180 nm CMOS technology and occupies 0.3 mm2.