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2017 International SoC Design Conference (ISOCC)最新文献

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A design of ultra-low noise LDO using noise reduction network techniques 采用降噪网络技术的超低噪声LDO设计
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368850
Hamed Abbasizadeh, B. S. Rikan, Thi Kim Nga Truong, Kwan-Tae Kim, Sungjin Kim, Dongsoo Lee, Kangyoon Lee
{"title":"A design of ultra-low noise LDO using noise reduction network techniques","authors":"Hamed Abbasizadeh, B. S. Rikan, Thi Kim Nga Truong, Kwan-Tae Kim, Sungjin Kim, Dongsoo Lee, Kangyoon Lee","doi":"10.1109/ISOCC.2017.8368850","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368850","url":null,"abstract":"This paper presents an ultra-low noise low-dropout (LDO) regulators for powering RF applications. The proposed LDO employs two internal noise reduction network at the output of the bandgap reference (BGR), and between output and feedback resistors node (VFB in Fig. 1) of LDO to achieve ultra-low noise at interest frequencies. The 5-bits controlled resistor ladder is adopted to compensate the process, voltage, and temperature (PVT) variations. The output voltage level of LDO can be from 1.05 V to 2.6 V with trimming step of 50 mV. The highest output noise of the LDO is 64.52 nV/VHz at 10 KHz. The proposed LDO is implemented in CMOS 55 nm technology with the die size of 480 μm × 330 μm.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114499939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Unequal protection approach for RLL-constrained LDPC coded recording system using deliberate flipping 基于故意翻转的rll约束LDPC编码记录系统的不等保护方法
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368811
Hong-Fu Chou, Chiu-Wing Sham
{"title":"Unequal protection approach for RLL-constrained LDPC coded recording system using deliberate flipping","authors":"Hong-Fu Chou, Chiu-Wing Sham","doi":"10.1109/ISOCC.2017.8368811","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368811","url":null,"abstract":"For alleviating Run-Length-Limited (RLL) code, the deliberate flipping approach imposes some bit errors before recording in order to meet the RLL constraint. However, high coding rate of recording system limits the correcting capability of RLL flipping errors. In this paper, we propose a decoding scheme using Unequal Protection (UEP) Low-Density Parity-Check (LDPC) code by means of regular inter-leaver to confine the occurrence of flipping errors into a section of codeword. Specified section with flipping errors are attributed to the high degree nodes with high error protection capability. Iterative decoding within several iterations can solve the hard errors at the reading side. Experimental results reveal that our approach has a better BER performance compared to the recording system with RLL code. Experimental results show that our proposed scheme can efficiently exploit the correction capability to recover flipping bits.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122095017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 14nm FinFET analog baseband SOC for multi-mode cellular applications with tri-band carrier aggregation 14nm FinFET模拟基带SOC，用于具有三频带载波聚合的多模蜂窝应用
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368772
Byungki Han, Jongwoo Lee, Seunghyun Oh, Jaekwon Kim, Eswar Mamidala, T. Cho
{"title":"A 14nm FinFET analog baseband SOC for multi-mode cellular applications with tri-band carrier aggregation","authors":"Byungki Han, Jongwoo Lee, Seunghyun Oh, Jaekwon Kim, Eswar Mamidala, T. Cho","doi":"10.1109/ISOCC.2017.8368772","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368772","url":null,"abstract":"This paper presents a power and area efficient ABB solution implemented in 14nm FinFET process for a cellular baseband SOC which supports tri-band RX CA and dual-band TX CA. 12bit RXADCs are implemented using ADC reference sharing capacitor with sampling rate up to 150MS/s for a single-LO contiguous intra-band CA. An oversampling SAR architecture provides reconfigurable mode and effective blocker sensing up to Nyquist bandwidth. 12bit TXDACs support up to 250MS/s speed with more than 80dB SFDR. A common-mode calibration technique is proposed to provide effective matching between TXDAC and RF transmitter.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116677818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology 多通道多千兆PRBS发生器，内置时钟，采用0.18 μm CMOS技术
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368893
Chi-Hsien Wu, Jau‐Ji Jou, Hsin-Wen Ting, Shao-I Chu, Bing-Hong Liu
{"title":"Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology","authors":"Chi-Hsien Wu, Jau‐Ji Jou, Hsin-Wen Ting, Shao-I Chu, Bing-Hong Liu","doi":"10.1109/ISOCC.2017.8368893","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368893","url":null,"abstract":"In this paper, a parallel pseudo-random bit sequence (PRBS) generator circuit with a built-in clock was designed in 0.18μm CMOS Technology. For high-speed operation, the current-mode logic (CML) was used in the circuit. In the PRBS generator, four-channel 2-Gb/s and two-channel 4-Gb/s PRBS signals can be generated. The power consumption of the chip is 554.3-mW at 1.8-V of power supply, and the chip area is 1.196×1.01-mm2. The PRBS generator can be suitable in multi-level modulation and multi-channel transmission tests.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124472847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Chaotic circuits network with scale-free coupling distribution 无标度耦合分布的混沌电路网络
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368838
Y. Uwate, Y. Nishio
{"title":"Chaotic circuits network with scale-free coupling distribution","authors":"Y. Uwate, Y. Nishio","doi":"10.1109/ISOCC.2017.8368838","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368838","url":null,"abstract":"In this study, we investigate synchronization observed in chaotic circuits network with scale-free coupling distribution. The network topology is inspired from real brain network. Here, we consider the network which consists of two modules including connector and provincial hubs. We confirm several clustering patterns from the proposed system.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127609246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of RF narrow band frequency synthesizer for LoRaWAN system LoRaWAN系统中射频窄带频率合成器的实现
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368868
Dong-Shik Kim, Won‐Sang Yoon, S. Chai
{"title":"Implementation of RF narrow band frequency synthesizer for LoRaWAN system","authors":"Dong-Shik Kim, Won‐Sang Yoon, S. Chai","doi":"10.1109/ISOCC.2017.8368868","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368868","url":null,"abstract":"A narrowband frequency synthesizer has been designed and fabricated to generate two bands of 868MHz(Europe) and 915MHz(North America) with a same chip. It will be applied as the LoRaWAN system. Measurement results show that the frequency synthesizer has bandwidth of 1,670 ∼ 1,972MHz(about 16.57% center frequency ratio), and low phase noise characteristics of −83.74dBc/Hz at 50μA charge pump output current and −86.81dBc/Hz at 300μA charge pump output current on 100KHz offset.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128196040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-area implementations of concurrent error detection logarithmic processors 并发错误检测对数处理器的低面积实现
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368833
Tso-Bing Juang, Ying-Ren Lee
{"title":"Low-area implementations of concurrent error detection logarithmic processors","authors":"Tso-Bing Juang, Ying-Ren Lee","doi":"10.1109/ISOCC.2017.8368833","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368833","url":null,"abstract":"In this paper, low-area implementations of concurrent error detection (CED) logarithmic processors are proposed. By adopting our logarithmic/anti-logarithmic converters with same functions having different architectures, the proposed schemes can perform logarithm-based multiplications/divisions with CED ability. Simulation results show that our proposed CED logarithmic processors can outperform conventional multipliers/dividers in terms of delay and area, which are more suitable for real-time computations with CED ability.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131719500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-performance RF-interconnect for 3D stacked memory 用于3D堆叠存储器的高性能rf互连
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368793
Ahmed Alzahmi, Nahid Mirzaie, Chung-Ching Lin, Insoo Kim, Gyung-Su Byun
{"title":"High-performance RF-interconnect for 3D stacked memory","authors":"Ahmed Alzahmi, Nahid Mirzaie, Chung-Ching Lin, Insoo Kim, Gyung-Su Byun","doi":"10.1109/ISOCC.2017.8368793","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368793","url":null,"abstract":"A high-performance 3D RF transceiver with improved through-silicon via (TSV) geometry and matching for future 3D stacked memory has been introduced. It utilizes optimization method to achieve impedance matching and maximize signal integrity. TSV is accurately modeled using 3D EM solver tool (HFSS) with the matching network to generate S-parameter accurately. The proposed transceiver scheme is simulated in 65nm CMOS technology at 1V. The results show that the whole structure consumes 11.32mW and accomplishes data rate of 4Gb/s/pin.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134647356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Clothing-based wearable sensors for unobtrusive interactions with mobile devices 基于衣服的可穿戴传感器，用于与移动设备进行不显眼的交互
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368837
V. Nanjappan, Hai-Ning Liang, Kim Lau, Jaemin Choi, Kyung Ki Kim
{"title":"Clothing-based wearable sensors for unobtrusive interactions with mobile devices","authors":"V. Nanjappan, Hai-Ning Liang, Kim Lau, Jaemin Choi, Kyung Ki Kim","doi":"10.1109/ISOCC.2017.8368837","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368837","url":null,"abstract":"The clothing materials are ubiquitous part of our everyday life for thousands of years. However, despite this they have largely not been considered as an input surface in human device interactions, but that is until more recently as today's developments of wearable sensors, that are small and flexible in nature, have open this platform. The clothing materials' shape-changing nature enables the users to perform gestures (e.g., bend or stretch) not possible when compared to the interaction methods of flat touchscreens of mobile devices. In addition, the clothing-based interfaces by default have the unique advantage of being placed anywhere on the body and always being with the wearers and their devices. In this paper, we validate the use of clothing-based wearable sensors to support interacting with mobile devices and present some challenges to be overcome for clothing-based interfaces to be adopted more widely.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127404900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An efficient built-in self-repair scheme for area reduction 一个有效的内置自我修复方案，面积减少
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368791
Keewon Cho, Young-woo Lee, Sungyoul Seo, Sungho Kang
{"title":"An efficient built-in self-repair scheme for area reduction","authors":"Keewon Cho, Young-woo Lee, Sungyoul Seo, Sungho Kang","doi":"10.1109/ISOCC.2017.8368791","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368791","url":null,"abstract":"As memory densities have drastically increased, memory faults have become the major factor of the decline in the yield. One powerful solution is built-in redundancy analysis (BIRA) which repairs faulty cells with spare lines. However, area overhead of BIRA should be carefully considered because a chip area is limited. In order to maximize the yield and minimize area overhead simultaneously, this paper proposes an efficient built-in self-repair (BISR) scheme. The proposed scheme performs the memory test process twice, so that faulty addresses can be stored efficiently. Experimental results show that the proposed BIRA can obtain optimal repair rate with very small area overhead.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115932976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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