High-performance RF-interconnect for 3D stacked memory

Abstract

A high-performance 3D RF transceiver with improved through-silicon via (TSV) geometry and matching for future 3D stacked memory has been introduced. It utilizes optimization method to achieve impedance matching and maximize signal integrity. TSV is accurately modeled using 3D EM solver tool (HFSS) with the matching network to generate S-parameter accurately. The proposed transceiver scheme is simulated in 65nm CMOS technology at 1V. The results show that the whole structure consumes 11.32mW and accomplishes data rate of 4Gb/s/pin.