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2017 International SoC Design Conference (ISOCC)最新文献

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Building block multi-chip systems using inductive coupling through chip interface 通过芯片接口使用电感耦合构建块多芯片系统
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368842
H. Amano, T. Kuroda, Hiroshi Nakamura, K. Usami, Masaaki Kondo, Hiroki Matsutani, M. Namiki
{"title":"Building block multi-chip systems using inductive coupling through chip interface","authors":"H. Amano, T. Kuroda, Hiroshi Nakamura, K. Usami, Masaaki Kondo, Hiroki Matsutani, M. Namiki","doi":"10.1109/ISOCC.2017.8368842","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368842","url":null,"abstract":"A building block computing system is consisting of multiple chips connecting with inductive coupling wireless through chip interconnect. Like building Lego blocks, various types of systems can be built by stacking different types of chips. In order to develop such systems, several techniques are investigated in the project: that is, inductive coupling wireless through chip interface, low power circuit technologies, autonomous interconnection network architectures, thermal dissipation and building block operating system. Here, the overview of the project and a prototype system are introduced.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117351575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A highly linear DPOTA-based configurable analog front-end for EXG (EEG, ECG, and EMG) 一个高度线性的基于dpota的可配置模拟前端，用于EXG (EEG, ECG和EMG)
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368914
M. B. Elamien, S. Mahmoud
{"title":"A highly linear DPOTA-based configurable analog front-end for EXG (EEG, ECG, and EMG)","authors":"M. B. Elamien, S. Mahmoud","doi":"10.1109/ISOCC.2017.8368914","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368914","url":null,"abstract":"This paper presents a digitally controllable analog front-end (AFE) for a portable EEG, ECG, and EMG detection systems. It consists of a low-pass filter (LPF) and two programmable gain amplifiers (PGAs). The proposed AFE is based on a highly linear digitally programmable fully differential operational transconductance amplifiers (DPOTAs). The transconductance of the DPOTA can be controlled, from 25 nA/V to 400 nA/V, by 4-bit digital word. The proposed AFE is designed and simulated in 90 nm CMOS technology. The LPF cutoff frequency can be adjusted to 107 Hz, 257 Hz and 537 Hz which is suitable for EEG, ECG, and EMG, respectively. The gain of the PGA is tuned from 0 dB to 70 dB with 5 dB steps.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116190768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low power 2.4 GHz quadrature local oscillator buffer for Bluetooth low energy applications 低功耗2.4 GHz正交本地振荡器缓冲器，用于蓝牙低功耗应用
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368874
Sinyoung Kim, Taejong Kim, K. Kwon
{"title":"A low power 2.4 GHz quadrature local oscillator buffer for Bluetooth low energy applications","authors":"Sinyoung Kim, Taejong Kim, K. Kwon","doi":"10.1109/ISOCC.2017.8368874","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368874","url":null,"abstract":"In this paper, a low power 2.4 GHz quadrature local oscillator (LO) buffer for Bluetooth low energy applications is proposed. A proposed quadrature LO buffer employs the transconductor-type IQ quadrature generator with a gain/phase mismatch compensator and generates accurate quadrature signals at the 2.4 GHz frequency with parasitic capacitances. The proposed LO buffer can minimize the power consumption of the LO path because the block generating quadrature signals such as a divider-by-2, a poly-phase filter, and a quadrature VCO can be removed from the LO path. The prototype is realized in CMOS 65 nm process. The LO buffer achieves simulated voltage gain of 6.5 dB and generates accurate quadrature signals while consuming 2 mA at the supply voltage of 1 V.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"36 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116409308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High resolution tactile sensing with silicon MEMS sensors for measurement of fingertip sensation 高分辨率触觉传感与硅MEMS传感器测量指尖的感觉
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368807
H. Takao
{"title":"High resolution tactile sensing with silicon MEMS sensors for measurement of fingertip sensation","authors":"H. Takao","doi":"10.1109/ISOCC.2017.8368807","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368807","url":null,"abstract":"In this paper, novel semiconductor silicon based MEMS tactile sensors for measurement of fingertip sensation and their high resolution detection ability of surface texture are presented. All the device structure is made from silicon single crystal layer on SOI wafer. The contactor of tactile sensor is designed to have similar size and cross-section with a human's fingerprint. Two-axis movements of a contactor tip are independently detected to obtain the real vibrating motion of a finger print under active sensing (sweeping) motion of fingertip. On the other hand, macro-area tactile sensors of “overall contact pressure” and “macro-area sliding friction” are also integrated on the same chip, since combination of micro and macro tactile information is important in human's fingertip tactile sensation. The multiple detection abilities will be very powerful for understanding how humans recognize and distinguish objects using their fingertip skin sensation. As an example of original application, “visualization of cloth surface texture” is demonstrated.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123224181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low power BCH decoder using early termination scheme for WBAN standard 低功耗BCH解码器采用早期终止方案的WBAN标准
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368884
Seo Lin Jeong, M. Sunwoo
{"title":"Low power BCH decoder using early termination scheme for WBAN standard","authors":"Seo Lin Jeong, M. Sunwoo","doi":"10.1109/ISOCC.2017.8368884","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368884","url":null,"abstract":"This paper presents a (63, 51) BCH decoder for the IEEE 802.15.6 wireless body area network (WBAN) standard. WBAN is applied to medical and non-medical devices that require short-range communications for human body. To reduce power consumption, the proposed BCH decoder uses an early termination scheme for the syndrome computation and Chien search, which can correct errors earlier. The proposed (63, 51) BCH decoder is implemented using the Samsung 65-nm CMOS standard cell library. Implementation results show that power consumption decreased to 45.86% compared to the case without the ET scheme at SNR = 7 dB.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122151705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High DC gain and wide output swing class-C inverter 高直流增益和宽输出摆幅c类逆变器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368823
Yaya Chen, Yan Han, Shifeng Zhang, Tianlin Cao, Xiaoxia Han, R. Cheung
{"title":"High DC gain and wide output swing class-C inverter","authors":"Yaya Chen, Yan Han, Shifeng Zhang, Tianlin Cao, Xiaoxia Han, R. Cheung","doi":"10.1109/ISOCC.2017.8368823","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368823","url":null,"abstract":"A gain-boost class-C inverter that simultaneously targets high DC gain and wide output swing is proposed in this study. Unlike those of the traditional gain-boost class-C inverter, the input transistors of the proposed gain-boost circuit for the PMOS cascode circuit are n type, whereas those for the NMOS cascode circuit are p type. Consequently, the output swing of the proposed gain-boost class-C inverter is unrestricted by the gain-boost circuit, and thus, a wide output swing can be achieved. A self-cascode structure is also adopted for the gain-boost circuit, thereby allowing it to obtain high DC gain. When compared with the traditional gain-boost class-C inverter with the same input transistor size, power consumption, and load capacitance, simulation results show that the proposed gain-boost class-C inverter improves DC gain by over 35% and boost output swing by over 20%.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126184163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Continuous-time delta-sigma modulator with an upfront passive-RC low-pass network 具有前置无源rc低通网络的连续时间δ - σ调制器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368776
Daxiang Li, Yang Zhang, D. Basak, K. Pun
{"title":"Continuous-time delta-sigma modulator with an upfront passive-RC low-pass network","authors":"Daxiang Li, Yang Zhang, D. Basak, K. Pun","doi":"10.1109/ISOCC.2017.8368776","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368776","url":null,"abstract":"A power-efficient third-order single-bit continuous-time Delta-Sigma modulator (CTDSM) with an upfront low-pass network (LPN) is presented. The passive LPN functions as an adder and a filter that realizes a noise transfer function zero and reduces the signal swing at the input of the subsequent active integrator. Transistor-level simulation results in 0.18μm CMOS show that the proposed CTDSM achieves 71.1-dB SNDR over a bandwidth of 2 MHz with a sampling frequency of 256 MHz, while consuming 124.5 μW power from a 1.8-V supply.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124667880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS 55nm CMOS的6位1.6-GS/s多米诺sar ADC
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368860
Yung-Hui Chung, Wei-Shu Rih
{"title":"A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS","authors":"Yung-Hui Chung, Wei-Shu Rih","doi":"10.1109/ISOCC.2017.8368860","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368860","url":null,"abstract":"This paper presents a 6-bit 1.6-GS/s SAR ADC incorporating a domino-comparator architecture. The proposed domino-SAR architecture effectively speed up ADC operation. To further fasten the operating speed, a ping-pong operation is applied to achieve 1.6-GS/s. To against PVT variations, an adaptive sampler is proposed to adjust the allocated conversion time automatically. The ADC was implemented in 55nm LP CMOS. It consumes 5 mW from a 1.2-V supply. At Nyquist-rate, the simulated SNDR and SFDR are 35.4 and 52 dB respectively. Its ENOB is 5.6 bits, equivalent to a FOM of 64 fJ/conv.-step.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128694208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analog front-end for EMG acquisition system 模拟前端肌电信号采集系统
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368825
Bum-Sik Chung, Hyeong-Kyu Kim, Kang-Il Cho, Ho-Jin Kim, G. Ahn
{"title":"Analog front-end for EMG acquisition system","authors":"Bum-Sik Chung, Hyeong-Kyu Kim, Kang-Il Cho, Ho-Jin Kim, G. Ahn","doi":"10.1109/ISOCC.2017.8368825","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368825","url":null,"abstract":"This paper presents a 4-channel analog front-end (AFE) for Electromyogram (EMG) acquisition systems. Each input channel consists of a chopper-stabilized instrumentation amplifier (IA) and a low-pass filer (LPF). A 15-bit analog-to-digital converter (ADC) with a buffer amplifier is shared with four input channels through multiplexer. An incremental ADC with a 1.5-bit second-order feed-forward topology is employed to achieve 15-bit resolution. The prototype AFE is fabricated in a 0.18 μm CMOS process with an active die area of 1.5 mm2. It achieves 3.2 μVrms input referred noise with a gain of 40 dB and a cutoff frequency of 500 Hz for LPF while consuming 3.713 mW from a 1.8V supply.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128941606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
HV voltage sensor for 16 series li-ion battery cells using chopper stabilized amplifier 采用斩波稳定放大器的16串联锂离子电池高压电压传感器
2017 International SoC Design Conference (ISOCC) Pub Date : 2017-11-01 DOI: 10.1109/ISOCC.2017.8368849
Tzung-Je Lee, Guan-Jhang Li
{"title":"HV voltage sensor for 16 series li-ion battery cells using chopper stabilized amplifier","authors":"Tzung-Je Lee, Guan-Jhang Li","doi":"10.1109/ISOCC.2017.8368849","DOIUrl":"https://doi.org/10.1109/ISOCC.2017.8368849","url":null,"abstract":"This paper proposes a HV voltage sensor for the 16 series Li-ion battery cells. In order to achieve low offset and low noise, the chopper stabilized technique is used for the OPA design. Besides, 9 resistor networks are employed to avoid the HV hazard caused by the HV signal of the 16 series battery cells. The proposed design is implemented using a typical 0.25 um 1P3M 60V BCD process. Based on HSPICE simulation results, the gate oxide overstress caused by the HV signal is avoided. Moreover, the detection error is only 0.404 mV.","PeriodicalId":248826,"journal":{"name":"2017 International SoC Design Conference (ISOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128890795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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